Patents by Inventor Masao Taguchi

Masao Taguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200401351
    Abstract: In a data storage control device for writing data into a first memory that is non-volatile memory, an information receipt unit receives voltage-related information from a power source control device. A condition determination unit determines whether a voltage condition is satisfied. When the condition determination unit determines that the voltage condition is satisfied during execution of a writing process, a memory controller determines whether a predetermined storage condition is satisfied. When the storage condition is not satisfied, the memory controller executes a first response process of withdrawing writing residual data into the first memory but setting a validity flag as invalid. When the storage condition is satisfied, the memory controller executes a second response process of writing the residual data into the first memory.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 24, 2020
    Inventors: Akiyo TAGUCHI, Masao KIMURA
  • Patent number: 10723494
    Abstract: A paper sheet bundling apparatus includes: a reel unit, in which a tape roll is set, configured to rotate the tape roll in a direction in which the tape is fed, and a direction in which the tape is wound; a tape transport unit, having a transport path provided between the reel unit and a tape bundling unit, configured to transport the tape, along the transport path, to supply the tape to the tape bundling unit when the tape bundling unit performs bundling, and to cause, when the tape bundling unit does not perform bundling, the tape to be in a stand-by state in which the tape is arranged continuously along the transport path; and specific operation execution means for executing, at a predetermined time, a specific operation of reducing tensile force in the tape arranged continuously along the transport path, when the tape bundling unit does not perform bundling.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 28, 2020
    Assignee: GLORY LTD.
    Inventors: Kiyoaki Kobayashi, Toshihiko Kobayashi, Yoshikatsu Mizushima, Hitoshi Kobayashi, Takahiko Taguchi, Masao Okamura, Atsushi Nagase
  • Patent number: 9418742
    Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 16, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
  • Patent number: 9171612
    Abstract: A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 27, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Masao Taguchi
  • Publication number: 20150054349
    Abstract: Wirelessly supplying power is rapidly changed by a switching circuit 11 selectively exciting a magnetic field coupling resonance circuit of L1 and C1 for wireless power supply by use of a resonant frequency of the resonance circuit and its ?-divided frequency. A large power is supplied in the case of excitation at the resonant frequency, and in the case of excitation at the ?-divided frequency, a small power is supplied. A wireless power supply device with a high power conversion efficiency, with less unwanted radiation, and capable of rapidly changing supplying power can thereby be provided.
    Type: Application
    Filed: February 4, 2013
    Publication date: February 26, 2015
    Inventors: Hiroki Ishikuro, Tadahiro Kuroda, Masao Taguchi
  • Publication number: 20140177339
    Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.
    Type: Application
    Filed: September 27, 2013
    Publication date: June 26, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Naoharu SHINOZAKI, Masao TAGUCHI, Takahiro HATADA, Satoru SUGIMOTO, Satoshi SAKURAKAWA
  • Patent number: 8553459
    Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
  • Publication number: 20130105874
    Abstract: A semiconductor device includes a gate electrode provided on a channel region in a semiconductor material layer having one type through a second insulating film; a capacitor electrode portion integrally formed with the gate electrode on the gate electrode; and a first electrode laterally surrounding the capacitor electrode portion through a first insulating film.
    Type: Application
    Filed: December 28, 2011
    Publication date: May 2, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Takeo FUJII, Masao TAGUCHI
  • Patent number: 8363466
    Abstract: At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (?3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 29, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Naoharu Shinozaki, Masao Taguchi, Satoru Sugimoto
  • Publication number: 20120319912
    Abstract: A device includes a first substrate that has a first antenna having a first loop and second loop that form loop shapes viewed in a planar projection; and a second substrate that has a second antenna having a third loop and fourth loop that form loop shapes viewed in the planar projection. The first substrate and the second substrate are disposed so that the first antenna and the second antenna face each other. At least when the first substrate and the second substrate operate, the first antenna and the second antenna are in a state that the first antenna and the second antenna are capable of being magnetically coupled.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 20, 2012
    Inventor: Masao TAGUCHI
  • Publication number: 20120051115
    Abstract: A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.
    Type: Application
    Filed: November 4, 2011
    Publication date: March 1, 2012
    Applicant: Spansion LLC
    Inventor: Masao Taguchi
  • Patent number: 8085615
    Abstract: A resistance changing memory unit cell includes a current control component operably coupled to a bit sense line, and a resistance changing memory element coupled between the current control component and a word line.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: December 27, 2011
    Assignee: Spansion LLC
    Inventor: Masao Taguchi
  • Patent number: 8064264
    Abstract: A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: November 22, 2011
    Assignee: Spansion LLC
    Inventors: Naoharu Shinozaki, Masao Taguchi, Akira Ogawa, Takuo Ito
  • Publication number: 20110261622
    Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 27, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
  • Patent number: 8014199
    Abstract: A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: September 6, 2011
    Assignee: Spansion LLC
    Inventor: Masao Taguchi
  • Patent number: 8008645
    Abstract: In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: August 30, 2011
    Assignee: Spansion LLC
    Inventor: Masao Taguchi
  • Publication number: 20110157978
    Abstract: At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (?3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 30, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Naoharu Shinozaki, Masao Taguchi, Satoru Sugimoto
  • Patent number: 7839671
    Abstract: In the present method of changing the state of a resistive memory device which is capable of adopting an erased, relatively higher resistance state and a programmed, relatively lower resistance state, the resistive memory device having first and second electrodes and an active layer between the first and second electrodes, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a first current limiting structure to change the resistive memory device from the erased, higher resistance state to the programmed, lower resistance state. Furthermore, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a second current limiting structure to change the resistive memory device from the programmed, lower resistance state to the erased, higher resistance state.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: November 23, 2010
    Assignee: Spansion LLC
    Inventor: Masao Taguchi
  • Patent number: 7782682
    Abstract: A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: August 24, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasurou Matsuzaki, Masao Taguchi
  • Patent number: 7755922
    Abstract: A resistance changing memory unit cell includes a resistance changing memory element coupled to a sense bit line and a diode coupled to the resistance changing memory element.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: July 13, 2010
    Assignee: Spansion LLC
    Inventor: Masao Taguchi