Patents by Inventor Masao Tanimoto

Masao Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10173606
    Abstract: A structure is for attaching an in-vehicle device including a display 20 standing on a dashboard 1 of a vehicle, and a controller 30 placed inside the dashboard 1. The structure includes a connecting bracket 40. The controller 30 is fixed to the dashboard 1. The controller 30 and the display 20 are connected together via the connecting bracket 40. The connecting bracket 40 is attachable to and detachable from the controller 30 and the display 20 independently.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 8, 2019
    Assignee: MAZDA MOTOR CORPORATION
    Inventors: Toshiteru Yoshimura, Yasuhiro Hidaka, Masaki Matsumoto, Masato Sadano, Masao Tanimoto, Takashi Fukumaru, Keizo Takahashi
  • Publication number: 20170282812
    Abstract: A structure is for attaching an in-vehicle device including a display 20 standing on a dashboard 1 of a vehicle, and a controller 30 placed inside the dashboard 1. The structure includes a connecting bracket 40. The controller 30 is fixed to the dashboard 1. The controller 30 and the display 20 are connected together via the connecting bracket 40. The connecting bracket 40 is attachable to and detachable from the controller 30 and the display 20 independently.
    Type: Application
    Filed: December 9, 2015
    Publication date: October 5, 2017
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Toshiteru YOSHIMURA, Yasuhiro HIDAKA, Masaki MATSUMOTO, Masato SADANO, Masao TANIMOTO, Takashi FUKUMARU, Keizo TAKAHASHI
  • Publication number: 20160121852
    Abstract: A defroster structure for a vehicle includes a duct guiding conditioned air sent out of an air conditioning unit to an outlet. The outlet is provided at a center of an upper surface of an instrument panel in a vehicle width direction along a lower end of a windshield. The duct includes an upstream portion, a downstream portion, and a curved portion curved and connecting the upstream and downstream portions together. An air passage in the duct has a partition dividing the air passage in a vehicle longitudinal direction into central and side air supply passages, which distribute air to a center and right and left sides of the windshield in the vehicle width direction. The partition extends from a point upstream of the curved portion of the duct to the downstream portion.
    Type: Application
    Filed: October 22, 2015
    Publication date: May 5, 2016
    Applicants: MAZDA MOTOR CORPORATION, DAIKYONISHIKAWA CORPORATION
    Inventors: Toshiteru YOSHIMURA, Masato SADANO, Masao TANIMOTO
  • Patent number: 6392270
    Abstract: In a semiconductor memory device, first insulating films are formed on a semiconductor substrate. Element isolating layers are formed on the semiconductor substrate for isolating element forming regions set at regular intervals in the semiconductor substrate, such that the upper surface of the element isolating layers are located at a higher level than the upper surface of the semiconductor substrate. First conductive layers are formed at regular intervals on the first insulating films. A second insulating film is formed on the element isolating layers and the first insulating film. A second conductive layer, which has a lower surface with irregularities corresponding to the configurations of the element isolating layers and the first conductive layer, and a flat upper surface irrespective of the configurations of the element isolating films and the first conductive layer, is formed on the second insulating film.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: May 21, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Tanimoto, Seiichi Mori
  • Publication number: 20020025630
    Abstract: In a semiconductor memory device, first insulating films are formed on a semiconductor substrate. Element isolating layers are formed on the semiconductor substrate for isolating element forming regions set at regular intervals in the semiconductor substrate, such that the upper surface of the element isolating layers are located at a higher level than the upper surface of the semiconductor substrate. First conductive layers are formed at regular intervals on the first insulating films. A second insulating film is formed on the element isolating layers and the first insulating film. A second conductive layer, which has a lower surface with irregularities corresponding to the configurations of the element isolating layers and the first conductive layer, and a flat upper surface irrespective of the configurations of the element isolating films and the first conductive layer, is formed on the second insulating film.
    Type: Application
    Filed: October 4, 1999
    Publication date: February 28, 2002
    Inventors: MASAO TANIMOTO, SEICHI MORI
  • Patent number: 5981381
    Abstract: In a semiconductor memory device, first insulating films are formed on a semiconductor substrate. Element isolating layers are formed on the semiconductor substrate for isolating element forming regions set at regular intervals in the semiconductor substrate, such that the upper surface of the element isolating layers are located at a higher level than the upper surface of the semiconductor substrate. First conductive layers are formed at regular intervals on the first insulating films. A second insulating film is formed on the element isolating layers and the first conductive layer. A second conductive layer, which has a lower surface with irregularities corresponding to the configurations of the element isolating layers and the first conductive layer, and a flat upper surface irrespective of the configurations of the element isolating films and the first conductive layer, is formed on the second insulating film.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Tanimoto, Seiichi Mori
  • Patent number: 5933731
    Abstract: The element separation region has a section on its surface, where the first resist pattern and second resist pattern overlap with each other. The overlapping section is not etched even while removing the dummy oxide films formed in the first and second regions divided by the element separation region. Therefore, a sufficient thickness of the element separation region is kept. Further, by providing the overlapping section, the formation of sources of generating dust, namely, fine recesses and projections on the element separation region, can be prevented if an masking error occurs. Consequently, the step of removing the dust generating sources is not necessary, thereby reducing the number of manufacturing steps.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Tanimoto, Norihisa Arai