Patents by Inventor Masaomi Emori

Masaomi Emori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411319
    Abstract: A semiconductor device includes a substrate having a first main surface and a second main surface opposite to the first main surface, and a first conductive layer covering the second main surface and including dendrites, wherein a via hole extending through the substrate and having an inner wall surface is formed in the substrate, and wherein the first conductive layer covers the inner wall surface.
    Type: Application
    Filed: March 7, 2023
    Publication date: December 21, 2023
    Inventors: Yuya TSUTSUMI, Masaomi EMORI
  • Patent number: 10446510
    Abstract: A process of forming a semiconductor apparatus is disclosed. The process includes steps of: depositing a first metal layer containing Ni in a back surface of a substrate, plating the back surface of the substrate so as to expose the first metal layer in a portion of the scribe line, depositing a third metal layer on the whole back surface of the substrate, and selectively removing the third metal layer in the portion of the scribe line so as to leave the first metal layer in the scribe line.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 15, 2019
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masaomi Emori
  • Publication number: 20180240765
    Abstract: A process of forming a semiconductor apparatus is disclosed. The process includes steps of: depositing a first metal layer containing Ni in a back surface of a substrate, plating the back surface of the substrate so as to expose the first metal layer in a portion of the scribe line, depositing a third metal layer on the whole back surface of the substrate, and selectively removing the third metal layer in the portion of the scribe line so as to leave the first metal layer in the scribe line.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 23, 2018
    Inventor: Masaomi Emori
  • Patent number: 7821134
    Abstract: A semiconductor device includes a lower pad layer, an insulating layer and an upper pad layer. The lower pad layer is provided on a semiconductor substrate. The insulating layer is away from a surrounding of the lower pad layer so that a space having a recess on a surface between the lower pad layer and the insulating layer is formed. The upper pad layer covers over the lower pad layer and the space, extends to an upper face of the insulating layer, and has an area larger than that of the lower pad layer.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: October 26, 2010
    Assignee: Eudyna Devices, Inc.
    Inventors: Norikazu Iwagami, Masaomi Emori
  • Patent number: 7754616
    Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer on a layer that is to be subjected to etching and contains at least one of silicon carbonate, silicon oxide, sapphire, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum nitride, the mask layer having an opening and including a nickel chrome film, a gold film, and a nickel film in this order when seen from the layer to be subjected to etching; and performing etching on the layer to be subjected to etching, with the mask layer serving as a mask.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: July 13, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Toshiyuki Kosaka, Masaomi Emori
  • Publication number: 20070207614
    Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer on a layer that is to be subjected to etching and contains at least one of silicon carbonate, silicon oxide, sapphire, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum nitride, the mask layer having an opening and including a nickel chrome film, a gold film, and a nickel film in this order when seen from the layer to be subjected to etching; and performing etching on the layer to be subjected to etching, with the mask layer serving as a mask.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Applicant: EUDYNA DEVICES INC.
    Inventors: Toshiyuki Kosaka, Masaomi Emori
  • Publication number: 20070200240
    Abstract: A semiconductor device includes a lower pad layer, an insulating layer and an upper pad layer. The lower pad layer is provided on a semiconductor substrate. The insulating layer is away from a surrounding of the lower pad layer so that a space having a recess on a surface between the lower pad layer and the insulating layer is formed. The upper pad layer covers over the lower pad layer and the space, extends to an upper face of the insulating layer, and has an area larger than that of the lower pad layer.
    Type: Application
    Filed: January 19, 2007
    Publication date: August 30, 2007
    Applicant: EUDYNA DEVICES INC.
    Inventors: Norikazu Iwagami, Masaomi Emori
  • Patent number: 6214639
    Abstract: A method of producing a semiconductor device including a step of forming separation grooves in scribing regions defined at boundary portions between a plurality of semiconductor-device forming portions formed on a top surface of a semiconductor substrate; a step of defining portions of the scribing regions in the semiconductor substrate as substrate connecting portions; and a step of cutting off the substrate connecting portions along the separation grooves, to thereby separate the plurality of semiconductor-device forming portions into chips. These production steps contribute to a higher working efficiency in a later assembling process and to improved mass-production.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: April 10, 2001
    Assignee: Fujitsu Limited
    Inventors: Masaomi Emori, Mitsuji Nunokawa, Kenichi Hiratsuka, Masanori Ishii, Hiroshi Kawakubo