Patents by Inventor Masaru Akino
Masaru Akino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11043434Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.Type: GrantFiled: January 15, 2020Date of Patent: June 22, 2021Assignee: ABLIC INC.Inventors: Hitomi Sakurai, Masaru Akino
-
Patent number: 10978414Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.Type: GrantFiled: February 19, 2020Date of Patent: April 13, 2021Assignee: ABLIC INC.Inventors: Shinjiro Kato, Masaru Akino
-
Publication number: 20200185343Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Inventors: Shinjiro Kato, Masaru AKINO
-
Publication number: 20200152529Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Applicant: ABLIC Inc.Inventors: Hitomi SAKURAI, Masaru AKINO
-
Patent number: 10607954Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.Type: GrantFiled: March 12, 2018Date of Patent: March 31, 2020Assignee: ABLIC INC.Inventors: Shinjiro Kato, Masaru Akino
-
Patent number: 10580708Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.Type: GrantFiled: February 14, 2018Date of Patent: March 3, 2020Assignee: ABLIC INC.Inventors: Hitomi Sakurai, Masaru Akino
-
Patent number: 10388618Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.Type: GrantFiled: February 11, 2019Date of Patent: August 20, 2019Assignee: ABLIC Inc.Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
-
Publication number: 20190189575Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Inventors: Takeshi MORITA, Shinjiro Kato, Masaru Akino, Yukihiro Imura
-
Patent number: 10297562Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.Type: GrantFiled: March 8, 2018Date of Patent: May 21, 2019Assignee: ABLIC INC.Inventors: Kaku Igarashi, Shinjiro Kato, Hisashi Hasegawa, Masaru Akino, Yukihiro Imura
-
Patent number: 10249584Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.Type: GrantFiled: March 8, 2018Date of Patent: April 2, 2019Assignee: ABLIC INC.Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
-
Publication number: 20180269171Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.Type: ApplicationFiled: March 12, 2018Publication date: September 20, 2018Inventors: Shinjiro KATO, Masaru AKINO
-
Publication number: 20180269170Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.Type: ApplicationFiled: March 8, 2018Publication date: September 20, 2018Inventors: Kaku IGARASHI, Shinjiro KATO, Hisashi HASEGAWA, Masaru AKINO, Yukihiro IMURA
-
Publication number: 20180269169Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.Type: ApplicationFiled: March 8, 2018Publication date: September 20, 2018Inventors: Takeshi MORITA, Shinjiro KATO, Masaru AKINO, Yukihiro IMURA
-
Publication number: 20180240721Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.Type: ApplicationFiled: February 14, 2018Publication date: August 23, 2018Inventors: Hitomi SAKURAI, Masaru AKINO
-
Patent number: 9945912Abstract: In a Hall sensor in which a Hall element and elements serving as heat sources out of components of a circuit for driving the Hall element are arranged close to each other on a silicon substrate, two directions of control currents by spinning current for the Hall element are selected in a vector manner based on signals from temperature sensors arranged close to a periphery of the Hall element, thereby enabling the elimination of a magnetic offset caused by heat generation of the heat sources.Type: GrantFiled: November 17, 2015Date of Patent: April 17, 2018Assignee: SEIKO INSTRUMENTS INC.Inventors: Takaaki Hioka, Masaru Akino
-
Patent number: 9917055Abstract: A corrosion-resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. An array of intersecting metal lines forming windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent entry of moisture.Type: GrantFiled: March 10, 2016Date of Patent: March 13, 2018Assignee: SII Semiconductor CorporationInventors: Yukihiro Imura, Yoshitaka Kimura, Masaru Akino
-
Patent number: 9818691Abstract: A corrosion resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. A metal lattice having a plurality of windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. Alternatively, a metal array having a plurality of independent light-shielding portions may be disposed over the fuse elements to prevent the laser light from adversely affecting circuitry on the front surface side of the semiconductor device.Type: GrantFiled: March 10, 2016Date of Patent: November 14, 2017Assignee: SII Semiconductor CorporationInventors: Yukihiro Imura, Yoshitaka Kimura, Masaru Akino
-
Patent number: 9694523Abstract: A semiconductor device manufacturing apparatus for encapsulating with a resin a semiconductor chip includes upper and lower molds configured to receive therebetween a lead frame on which the semiconductor chip is mounted. A positioning pin provided to the lower mold is configured to be received by a positioning hole provided in the lead frame. Ejector pins provided in proximity to the positioning pin are arranged so as to be symmetrical with respect to the positioning pin.Type: GrantFiled: February 26, 2016Date of Patent: July 4, 2017Assignee: SII Semiconductor CorporationInventors: Yasuo Terui, Masaru Akino
-
Patent number: 9679835Abstract: A resin-encapsulated semiconductor device comprises a semiconductor chip mounted on a die pad. A plurality of leads each having an inner lead and an outer lead are arranged in spaced relation from the die pad with the inner leads facing the die pad. A metal plating layer is formed on top surfaces of the inner leads, and the inner leads are connected by metal wires to the semiconductor chip. An encapsulation resin encapsulates the semiconductor chip, die pad, metal wires and inner leads leaving the outer leads exposed. The outer edge of the metal plating layer coincides with the outer surface of the encapsulation resin and with the outer edge of the metal plating layer.Type: GrantFiled: June 17, 2015Date of Patent: June 13, 2017Assignee: SII Semiconductor CorporationInventors: Shinya Kubota, Masaru Akino
-
Publication number: 20160268196Abstract: Provided is a corrosion resistant semiconductor device including a fuse element that can be cut by laser light. In the semiconductor device, an upper portion of the fuse element is covered with a porous insulating film so that, when laser light radiated from a rear surface of a semiconductor substrate is collected at the fuse element, the fuse element may generate heat, expand, and rupture. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent moisture from coming therein.Type: ApplicationFiled: March 10, 2016Publication date: September 15, 2016Inventors: Yukihiro IMURA, Yoshitaka KIMURA, Masaru AKINO