Abstract: A light source device according to the present disclosure includes: a first terminal, a second terminal, a third terminal, and a fourth terminal; a first light-emitting element that is disposed in a first path from the first terminal to the second terminal, includes a first electrode of a first type and a second electrode of a second type coupled to the second terminal, and emits first basic color light; a second light-emitting element that is disposed in a second path from the second terminal to the third terminal, includes a first electrode of the first type coupled to the second terminal and a second electrode of the second type, and emits second basic color light; and a third light-emitting element that is disposed in a third path from the second terminal to the fourth terminal, includes a first electrode of the first type coupled to the second terminal and a second electrode of the second type, and emits third basic color light.

Abstract: A light source device according to the present disclosure includes: a first terminal, a second terminal, a third terminal, and a fourth terminal; a first light-emitting element that is disposed in a first path from the first terminal to the second terminal, includes a first electrode of a first type and a second electrode of a second type coupled to the second terminal, and emits first basic color light; a second light-emitting element that is disposed in a second path from the second terminal to the third terminal, includes a first electrode of the first type coupled to the second terminal and a second electrode of the second type, and emits second basic color light; and a third light-emitting element that is disposed in a third path from the second terminal to the fourth terminal, includes a first electrode of the first type coupled to the second terminal and a second electrode of the second type, and emits third basic color light.

Abstract: A comparator circuit according to the present disclosure includes a first switch section that selectively takes in a signal voltage, a second switch section that selectively takes in a control waveform, a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section, a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage, and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.

Abstract: A sample-and-hold circuit of the disclosure includes: a differential pair that includes a first MOS transistor and a second MOS transistor, in which respective source terminals of the first MOS transistor and the second MOS transistor are interconnected to a specified node, and an input signal is input to a gate terminal of the first MOS transistor; a capacitor that is coupled to a gate terminal of the second MOS transistor, and samples and holds the input signal; a switch transistor that has a source terminal coupled to the capacitor and the gate terminal of the second MOS transistor, and causes the capacitor to sample and hold the input signal upon application of a predetermined ON voltage; and an ON-voltage control transistor that couples a gate terminal of the switch transistor to the specified node when causing the input signal to be sampled and held.

Abstract: A comparator circuit according to the present disclosure includes: a first switch section that selectively takes in a signal voltage; a second switch section that selectively takes in a control waveform; a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section; a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage; and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.

Abstract: A comparator circuit according to the present disclosure includes: a first switch section that selectively takes in a signal voltage; a second switch section that selectively takes in a control waveform; a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section; a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage; and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.

Abstract: A sample-and-hold circuit of the disclosure includes: a differential pair that includes a first MOS transistor and a second MOS transistor, in which respective source terminals of the first MOS transistor and the second MOS transistor are interconnected to a specified node, and an input signal is input to a gate terminal of the first MOS transistor; a capacitor that is coupled to a gate terminal of the second MOS transistor, and samples and holds the input signal; a switch transistor that has a source terminal coupled to the capacitor and the gate terminal of the second MOS transistor, and causes the capacitor to sample and hold the input signal upon application of a predetermined ON voltage; and an ON-voltage control transistor that couples a gate terminal of the switch transistor to the specified node when causing the input signal to be sampled and held.

Abstract: A comparator circuit according to the present disclosure includes: a first switch section that selectively takes in a signal voltage; a second switch section that selectively takes in a control waveform; a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section; a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage; and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.