Abstract: A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.

Abstract: A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.

Abstract: Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information.

Abstract: A test apparatus tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the device under test generated from the device under test and detects a phase difference between the operational clock signal and the rate signal using the rate signal as a standard, a test signal generating section that generates a test signal to be supplied to the device under test in synchronization with the rate signal, a delaying section that delays the test signal in accordance with the phase difference to substantially synchronize the delayed signal with the operational clock signal, and a test signal supplying section that supplies the delayed test signal to the device under test.

Abstract: A test apparatus that tests a plurality of device under tests includes: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; an additional pattern storage section that previously stores therein an additional pattern to be added to the common pattern; and an each pattern adding section that reads the additional pattern for each of the device under tests based on a result signal outputted from the device under test and provides the additional pattern added with the common pattern to the device under test.

Abstract: Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information.

Abstract: There is provided a detection apparatus including a transition point detecting unit operable to receive the output signal to detect the point of transition, a timing comparing unit operable to detect the signal level of the output signal in front of or behind the point of transition in the output signal, and a correction unit operable to compensate the timing of the point of transition detected from the transition point detecting unit based on the signal level of the output signal detected from the timing comparing unit.

Abstract: There is provided a test apparatus for testing a memory under test that includes therein a plurality of blocks and one or more repairing columns.

Abstract: A multi-strobe generation apparatus for generating a multi-strobe has a plurality of strobes. The multi-strobe generation apparatus includes a shift clock generating section which outputs a shift clock generated by dividing a reference clock at a timing at which each strobe is generated, a strobe generating section for generating the multi-strobe corresponding to each leading or trailing edge of the reference clock, and an adjustment section for adjusting timing at which the strobe generating section generates each strobe based on the shift clock.

Abstract: There is provided a test apparatus for testing a memory under test that includes therein a plurality of blocks and one or more repairing columns.

Abstract: A slurry for molding an article is provided wherein a source powder including at least one of a ceramic powder and a metal powder is dispersed, introduced into a forming mold, cured in the forming mold to form the molded article, and at least a part of the forming mold is degraded or dissolved in releasing the molded article from the forming mold. The major components of the slurry include the source powder, a dispersion medium and a gellifying agent, wherein the dispersion medium and the gellifying agent each contain an organic compound having a reactive functional group such that the slurry is cured by a reaction between the organic compound in the dispersion medium and the organic compound in the gellifying agent.

Abstract: A multi-strobe apparatus for generating multi-strobe having a plurality of strobes is provided, wherein the multi-strobe apparatus includes a clock generating unit which is able to generate a signal for adjustment at a timing at which each of the plurality of strobes should be generated; a strobe generating circuit for generating the plurality of strobes; and an adjusting module for adjusting a timing of the strobe generating circuit's generating each of the strobes on the basis of the signal for adjustment.

Abstract: A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail memory unit includes a write time measuring section for measuring a write time required for writing said test data per each of said pages, an integrating section for integrating said write time across a plurality of said pages set in advance, and a judging section for judging whether or not said memory-under-test is defect-free by comparing a value integrated by said integrating section with an expected value set in advance. The integrating section further integrates said write time per page group having said predetermined number of pages. The judging section further judges whether or not said page group is defect-free based on an integral value of said write time per said page group.

Abstract: There is provided a test apparatus for testing a semiconductor device. The test apparatus includes a pattern generating section that sequentially reads and outputs waveform information to be used for testing the semiconductor device, where the waveform information is made up by a plurality, of pieces of data, a waveform generating section that generates a waveform based on the waveform information which is sequentially output from the pattern generating section, a match detecting section that detects, in response to a signal indicating a match detection request cycle output from the pattern generating section, whether an output signal output from the semiconductor device matches an expected value pattern, and an interrupt section that, when the match detecting section detects that the output signal matches the expected value pattern, terminates the match detection request cycle and causes the pattern generating section to output next waveform information.

Abstract: A test apparatus that tests a plurality of device under tests includes: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; an additional pattern storage section that previously stores therein an additional pattern to be added to the common pattern; and an each pattern adding section that reads the additional pattern for each of the device under tests based on a result signal outputted from the device under test and provides the additional pattern added with the common pattern to the device under test.

Abstract: There is provided a test apparatus that tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the device under test generated from the device under test and detects a phase difference between the operational clock signal and the rate signal using the rate signal as a standard, a test signal generating section that generates a test signal to be supplied to the device under test in synchronization with the rate signal, a delaying section that delays the test signal in accordance with the phase difference to substantially synchronize the delayed signal with the operational clock signal, and a test signal supplying section that supplies the delayed test signal to the device under test.

Abstract: A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configured with multi-phase pulses given the phase difference by a small amount in regard to the timing of the data and the timing of the reference clock. In addition, a glitch of the data is detected, and the quality of the semiconductor device to be tested is judged based on the phase difference and/or the glitch.

Abstract: There is provided a testing apparatus for testing a memory-under-test, having a pin electronics section for inputting/receiving signals to/from the memory-under-test, a pattern generating section for inputting a test pattern to the memory-under-test via the pin electronics section and a judging section for receiving an output signal of the memory-under-test via the pin electronics section to judge whether or not the memory-under-test is defect-free based on the output signal, wherein the pin electronics section has an internal circuit for inputting/receiving the signal to/from the memory-under-test, a first transmission line for connecting the internal circuit with the memory-under-test and a first switch for connecting the first transmission line with earth potential when the memory-under-test is not tested and for disconnecting the first transmission line from the earth potential in testing the memory-under-test.

Abstract: A testing apparatus for performing a setup testing or a hold testing on a device under test (“DUT”) storing a given data signal according to a given clock signal is provided, wherein the testing apparatus includes a timing generating unit for generating sequentially a plurality of timing signals having different timings during the setup testing or the hold testing on the basis of a fist offset value given before starting the setup testing or the hold testing; a pattern generating unit for generating the clock signal and the data signal; a pattern formatting unit for shifting the phase of the data signal with respect to the clock signal sequentially according to the timing signals sequentially generated and providing the DUT with the clock signal and the phase-shifted data signal sequentially; and a determining module for acquiring a setup time or a hold time of the DUT on the basis of storage data which are the data signals stored by the DUT.

Abstract: There is provided a timing generator generating a timing signal of a predetermined period. The timing generator includes a set/reset latch, a set unit supplying the set signal, and a reset unit supplying the reset signal, in which the set unit includes: a first variable delay circuit that delays a given reference clock to output a first set signal; a second variable delay circuit that delays the given reference clock to output a second set signal having a phase different from the first set signal; an OR circuit that computes a logical sum of the first set signal and the second set signal to generate the set signal; and a third variable delay circuit that delays the set signal output from the OR circuit to adjust a skew between the set signal and the reset signal.