Abstract: Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section.

Abstract: Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.

Abstract: Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.

Abstract: There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.

Abstract: There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers.

Abstract: A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test, the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

Abstract: A test apparatus that tests a device under test by communicating with the device under test using packets that each include one or more command sequences, comprising a transmitting/receiving section that transmits and receives the packets to and from the device under test based on packet sequence information designating an order in which the packets are transmitted and received between the device under test and each pin of the test apparatus, and a display section that displays information indicating the packets transmitted and received between the device under test and each pin of the test apparatus, arranged in time sequence. The display section displays information of each packet transmitted or received in parallel on a time axis set in common for each pin of the test apparatus. Each packet includes identification information identifying a packet type, and the display section displays information including the identification information of each packet.

Abstract: Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.

Abstract: There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.

Abstract: There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a packet communication program generating section that generates from the packet sequence a packet communication program for a test, where the packet communication program is to be executed by the test apparatus to communicate packets included in the packet sequence between the test apparatus and the device under test, and a testing section that executes the packet communication program to test the device under test by communicating the packets between the test apparatus and the device under test.

Abstract: Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.

Abstract: Provided is a test apparatus that tests a device under test, comprising an upper sequencer that sequentially designates packets transmitted to and from the device under test, by executing a test program for testing the device under test; a packet data sequence storing section that stores a data sequence included in each of a plurality of types of packets; and a lower sequencer that reads, from the packet data sequence storing section, a data sequence of a packet designated by the upper sequencer and generates a test data sequence used for testing the device under test.

Abstract: There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers.

Abstract: Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section.

Abstract: There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a packet communication program generating section that generates from the packet sequence a packet communication program for a test, where the packet communication program is to be executed by the test apparatus to communicate packets included in the packet sequence between the test apparatus and the device under test, and a testing section that executes the packet communication program to test the device under test by communicating the packets between the test apparatus and the device under test.

Abstract: Provided is a test apparatus that tests a device under test, comprising an upper sequencer that sequentially designates packets transmitted to and from the device under test, by executing a test program for testing the device under test; a packet data sequence storing section that stores a data sequence included in each of a plurality of types of packets; and a lower sequencer that reads, from the packet data sequence storing section, a data sequence of a packet designated by the upper sequencer and generates a test data sequence used for testing the device under test.

Abstract: There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.

Abstract: There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.

Abstract: A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test; the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

Abstract: There is provided a test apparatus for testing a device under test. The test apparatus includes first and second period generators that respectively generate test period signals indicating test periods for testing the device under test, a plurality of input/output sections that are provided in correspondence with a plurality of terminals of the device under test, wherein each of the plurality of input/output sections, in accordance with a test period supplied thereto, outputs a test signal to a corresponding one of the plurality of terminals and receives an output signal output from the corresponding terminal, and a plurality of selecting sections that are provided in correspondence with the plurality of input/output sections, wherein each of the plurality of selecting sections selects one of the test period signals generated by the first and second period generators so as to be supplied to a corresponding one of the plurality of input/output sections.