Abstract: According to an embodiment, a server manages transaction settlement data generated by a first type of point-of-sale (POS) device and a second type of POS device. The server includes a storage device, a communication interface, and a processor. The communication interface receives first settlement data generated by a first POS device of the first type. The processor determines whether predetermined information is included with the first settlement data. The storage device stores the first settlement data only if the predetermined information is included. The communication interface receives second settlement data generated by a second POS device of the second type, the second settlement data not including the predetermined information. The storage device stores the second settlement data. The processor performs an accounting processing on the stored first and second settlement data.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: An LSI with built-in CPU includes a CPU core, an internal CPU bus connected to the CPU core, an external memory access-use external pin for accessing an external memory and a bus selector for outputting signals of the internal CPU bus to the external memory access-use external pin when the external memory is not being accessed.

Abstract: Ferromagnetic Fe-Ni alloy powders having the combination of a coercive force of 550-900 Oe (oersted) and a saturation flux density of 90-170 emu/g are provided by applying a nickel compound in a liquid to a particulate, oxygen-containing iron compound having an average particle length of 0.5-5 .mu.m and an average particle width of 0.02-0.5 .mu.m, and then drying and reducing the treated material to produce a metallic powder. The ferromagnetic powders are suitable for production of magnetic recording media because of the balanced magnetic properties.