Patents by Inventor Masaru Haraguchi
Masaru Haraguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021241Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a drive circuit coupled to a first line and a second line. In one aspect, the drive circuit is configured to apply, according to a first control signal having a first state, a data signal to either one of the first line or the second line to write data at a memory cell. In one aspect, the memory device includes a pre-charge circuit configured to set, according to a second control signal having a second state, voltages at the first line and the second line to a predetermined voltage level. In one aspect, the memory device includes an equalizer configured to electrically decouple the first line from the second line, according to the first control signal having the first state and the second control signal having the second state.Type: ApplicationFiled: January 30, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Masaru Haraguchi, Yoshisato Yokoyama, Yorinobu Fujino
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Publication number: 20220302021Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.Type: ApplicationFiled: June 1, 2022Publication date: September 22, 2022Applicant: AP Memory Technology Corp.Inventors: Wenliang CHEN, Jun GU, Masaru HARAGUCHI, Takashi KUBO, Chien-An YU, Chun Yi LIN
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Patent number: 11417628Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.Type: GrantFiled: September 1, 2020Date of Patent: August 16, 2022Assignee: AP Memory Technology CorporationInventors: Wenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien An Yu, Chun Yi Lin
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Patent number: 11380614Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.Type: GrantFiled: September 2, 2020Date of Patent: July 5, 2022Assignee: AP Memory Technology Corp.Inventors: Wenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien-An Yu, Chun Yi Lin
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Publication number: 20210398943Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.Type: ApplicationFiled: September 1, 2020Publication date: December 23, 2021Inventors: WENLIANG CHEN, JUN GU, MASARU HARAGUCHI, TAKASHI KUBO, CHIEN AN YU, CHUN YI LIN
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Patent number: 11200945Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.Type: GrantFiled: January 31, 2017Date of Patent: December 14, 2021Assignee: ZENTEL JAPAN CORPORATIONInventors: Takashi Kubo, Masaru Haraguchi, Takeshi Hamamoto, Kenichi Yasuda, Yasuhiko Tsukikawa, Hironori Iga
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Patent number: 11038012Abstract: In the present invention, lower electrodes (101, 102) are disposed at a period d1 in an X direction and at a period d2 in a Y direction. Upper electrodes (102) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the lower electrodes (101), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the lower electrodes (101). Each pair of a lower electrode (101) and an upper electrode (102), which face each other and capacitively couple with each other, form a capacitor cell (C). Cell terminals (103, 104) are disposed at the period (d1) in the X direction, disposed at the period (d2) in the Y direction, and respectively electrically connected to the lower electrodes (101) and the upper electrodes (102).Type: GrantFiled: April 28, 2017Date of Patent: June 15, 2021Assignees: AP Memory Technology Corp., AP Memory Technology (Hangzhou) Limited Co.Inventors: Masaru Haraguchi, Yoshitaka Fujiishi
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Patent number: 10991418Abstract: A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.Type: GrantFiled: March 6, 2017Date of Patent: April 27, 2021Assignee: ZENTEL JAPAN CORPORATIONInventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
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Patent number: 10978413Abstract: A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.Type: GrantFiled: December 3, 2019Date of Patent: April 13, 2021Assignee: AP MEMORY TECHNOLOGY CORP.Inventors: Masaru Haraguchi, Yoshitaka Fujiishi
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Publication number: 20210050410Abstract: A capacitor device includes: a substrate; an insulation film, disposed on the substrate; at least one capacitor unit cell, being covered by the insulation film on the substrate, the at least one capacitor unit cell having at least one first electrode and at least one second electrode disposed over the first electrode; an exposed conductive layer, disposed on the at least one capacitor unit cell and the insulation film, the exposed conductive layer having a first conductive pad formed on a first side of the exposed conductive layer and a second conductive pad formed on a second side different from the first side; wherein the first conductive pad and the second conductive pad are electrically connected to the at least one first electrodes and the at least one second electrodes of the at least one capacitor unit cell respectively.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Applicants: AP Memory Technology Corp., AP Memory Technology (Hangzhou) Limited Co.Inventors: Masaru HARAGUCHI, Yoshitaka FUJIISHI, Wenliang CHEN
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Publication number: 20200402951Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.Type: ApplicationFiled: September 1, 2020Publication date: December 24, 2020Inventors: WENLIANG CHEN, JUN GU, MASARU HARAGUCHI, TAKASHI KUBO, CHIEN AN YU, CHUN YI LIN
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Publication number: 20200402903Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Applicant: AP Memory Technology Corp.Inventors: Wenliang CHEN, Jun GU, Masaru HARAGUCHI, Takashi KUBO, Chien-An YU, Chun Yi LIN
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Patent number: 10818337Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.Type: GrantFiled: August 2, 2017Date of Patent: October 27, 2020Assignee: ZENTEL JAPAN CORPORATIONInventors: Bunsho Kuramori, Mineo Noguchi, Akihiro Hirota, Masahiro Ishihara, Mitsuru Yoneyama, Takashi Kubo, Masaru Haraguchi, Jun Setogawa, Hironori Iga
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Publication number: 20200135261Abstract: According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device.Type: ApplicationFiled: March 6, 2017Publication date: April 30, 2020Inventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
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Publication number: 20200105688Abstract: A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Inventors: Masaru HARAGUCHI, Yoshitaka FUJIISHI
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Publication number: 20200098853Abstract: In the present invention, lower electrodes (101, 102) are disposed at a period d1 in an X direction and at a period d2 in a Y direction. Upper electrodes (102) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the lower electrodes (101), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the lower electrodes (101). Each pair of a lower electrode (101) and an upper electrode (102), which face each other and capacitively couple with each other, form a capacitor cell (C). Cell terminals (103, 104) are disposed at the period (d1) in the X direction, disposed at the period (d2) in the Y direction, and respectively electrically connected to the lower electrodes (101) and the upper electrodes (102).Type: ApplicationFiled: April 28, 2017Publication date: March 26, 2020Applicants: ZENTEL JAPAN CORPORATION, AP Memory Technology (Hangzhou) Limited Co.Inventors: Masaru HARAGUCHI, Yoshitaka FUJIISHI
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Publication number: 20190378561Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.Type: ApplicationFiled: January 31, 2017Publication date: December 12, 2019Inventors: TAKASHI KUBO, MASARU HARAGUCHI, TAKESHI HAMAMOTO, KENICHI YASUDA, YASUHIKO TSUKIKAWA, HIRONORI IGA
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Publication number: 20190362774Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.Type: ApplicationFiled: August 2, 2017Publication date: November 28, 2019Inventors: Bunsho KURAMORI, Mineo NOGUCHI, Akihiro HIROTA, Masahiro ISHIHARA, Mitsuru YONEYAMA, Takashi KUBO, Masaru HARAGUCHI, Jun SETOGAWA, Hironori IGA
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Publication number: 20190198460Abstract: A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Masaru HARAGUCHI, Yoshitaka FUJIISHI
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Patent number: 9921638Abstract: The data processing system has: a plurality of hardware resources each having at least one standby mode; a control part for controlling execution of a task achieved by using, of the plurality of hardware resources, predetermined ones, and a working status of each hardware resource; and a power-source part for controlling supply of a power source to each hardware resource. The control part performs the scheduling of a scheduled execution time of the task based on information for determining a timing of executing the task, and calculates a standby time of the hardware resource based on a result of the scheduling. The control part compares the standby time with a break-even time depending on the standby mode, thereby deciding whether or not to cause each hardware resource to transition to the standby mode.Type: GrantFiled: September 29, 2014Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaru Haraguchi, Isamu Hayashi, Hiroyuki Kawai, Hideyuki Noda