Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.

Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.

Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.

Abstract: A tape carrier for electronic components is provided with enlarged regions along cut out lines defining the boundaries of the electronic component mount area. Provision is made for temporarily maintaining the cut out mount area substantially coplanar with remaining portions of the tape carrier. In the preferred embodiment, this is accomplished by way of an adhesive tape bridging the enlarged openings or by tabs or micro connectors bridging the enlarged openings. Thereafter, the mounts can be totally removed from the carrier film by severing the tape or the tabs. The enlarged regions facilitate the severance of the tape or tabs in an automated assembly line environment.

Abstract: A mounting apparatus for deploying a plurality of FPC tape carrier electronic component mounting structures having a plurality of cut out regions in a FPC tape carrier formed spatially along the length thereof, which regions define electronic component mounts. These cut out regions are contained within the confines of the FPC tape carrier and having a preformed substantially closed loop cut out boundary. Each of these cut out regions may contain at least one electronic component mount having a semiconductor integrated circuit chip electronic device electrically connected to at least one lead pattern formed on the carrier within the cut out region boundary. Slits or slit apertures are formed at one or more points along the cut out boundary. Securing attachment is provided at one or more points along the mount boundary, which are provided at the regions of the slits or slit apertures to secure the electronic component mounts with minimal connection to the body of the tape carrier.

Abstract: A FPC tape carrier electronic component mounting structure comprises a plurality of cut out regions in a FPC tape carrier formed spatially along the length thereof, which regions define electronic component mounts. These cut out regions are contained within the confines of the FPC tape carrier and having a preformed substantially closed loop cut out boundary. Each of these cut out regions may contain at least one electronic component mount comprising a semiconductor integrated circuit chip electronic device electrically connected to at least one lead pattern formed on the carrier within the cut out region boundary. Slits or slit apertures are formed at one or more points along the cut out boundary. Securing, attachment is provided at one or more points along the mount boundary, which are provided at the regions of the slits or slit apertures to secure the electronic component mounts with minimal connection to the body of the tape carrier.