Patents by Inventor Masaru Kido
Masaru Kido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9041093Abstract: The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.Type: GrantFiled: January 13, 2014Date of Patent: May 26, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu Tanaka, Ryota Katsumata, Hideaki Aochi, Masaru Kido, Masaru Kito, Mitsuru Sato
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Publication number: 20140124850Abstract: The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu TANAKA, Ryota KATSUMATA, Hideaki AOCHI, Masaru KIDO, Masaru KITO, Mitsuru SATO
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Patent number: 8659070Abstract: The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.Type: GrantFiled: September 17, 2009Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Ryota Katsumata, Hideaki Aochi, Masaru Kido, Masaru Kito, Mitsuru Sato
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Patent number: 8253187Abstract: A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.Type: GrantFiled: June 19, 2008Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kido, Hideaki Aochi, Mitsuru Sato, Yasuyuki Matsuoka
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Publication number: 20100052042Abstract: The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.Type: ApplicationFiled: September 17, 2009Publication date: March 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu TANAKA, Ryota KATSUMATA, Hideaki AOCHI, Masaru KIDO, Masaru KITO, Mitsuru SATO
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Publication number: 20080315296Abstract: A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.Type: ApplicationFiled: June 19, 2008Publication date: December 25, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu TANAKA, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kido, Hideaki Aochi, Mitsuru Sato, Yasuyuki Matsuoka
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Patent number: 7276750Abstract: A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.Type: GrantFiled: August 20, 2004Date of Patent: October 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Masaru Kido, Hideaki Aochi, Toshiharu Tanaka, Ryota Katsumata, Hideki Inokuma, Yoichi Takegawa
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Publication number: 20050145914Abstract: A semiconductor memory includes a semiconductor substrate; a capacitor arranged in a lower portion of the trench; a collar oxide film arranged on a side of the trench above the capacitor and having an upper collar member and a lower collar member, the upper collar member being thinner than the lower collar member so as to provide a height difference therebetween; a storage node arranged on a side of the collar oxide film; a select transistor provided on the semiconductor substrate and having a doped layer in contact with the collar oxide film; and a conductor portion arranged upon the storage node and the doped layer.Type: ApplicationFiled: July 16, 2004Publication date: July 7, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Toshiharu Tanaka, Hideaki Aochi, Masaru Kito, Masaru Kido
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Publication number: 20050101094Abstract: A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.Type: ApplicationFiled: August 20, 2004Publication date: May 12, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Masaru Kido, Hideaki Aochi, Toshiharu Tanaka, Ryota Katsumata, Hideki Inokuma, Yoichi Takegawa