Patents by Inventor Masaru Kito
Masaru Kito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138150Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Publication number: 20240102627Abstract: A road surface rendering device for rendering a road surface by illuminating an illumination region extending along a direction away from the road surface rendering device with light. The illumination region is divided into three regions of a left region, a central region, and a right region in a direction intersecting a longitudinal direction, an illuminance of the central region is largest.Type: ApplicationFiled: January 12, 2022Publication date: March 28, 2024Applicant: KOITO MANUFACTURING CO., LTD.Inventors: Yukiko Kitazawa, Masaru Sasaki, Koichi Tanabe, Ken Watanabe, Masanori Kito
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Patent number: 11903207Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: May 20, 2022Date of Patent: February 13, 2024Assignee: Kioxia CorporationInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 11903205Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: May 13, 2022Date of Patent: February 13, 2024Assignee: Kioxia CorporationInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20240008276Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: September 12, 2023Publication date: January 4, 2024Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Junya MATSUNAMI, Tomoko FUJIWARA, Hideaki AOCHI, Ryouhei KIRISAWA, Yoshimasa MIKAJIRI, Shigeto OOTA
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Patent number: 11844218Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: June 17, 2022Date of Patent: December 12, 2023Assignee: KIOXIA CORPORATIONInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 11792992Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: January 14, 2022Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20230146470Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritahle memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of colunmar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: December 30, 2022Publication date: May 11, 2023Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Patent number: 11574926Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: October 12, 2021Date of Patent: February 7, 2023Assignee: KIOXIA CORPORATIONInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Publication number: 20220328517Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: May 20, 2022Publication date: October 13, 2022Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Publication number: 20220320138Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Publication number: 20220302166Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: May 13, 2022Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Patent number: 11393840Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: December 11, 2019Date of Patent: July 19, 2022Assignee: KIOXIA CORPORATIONInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 11374021Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: January 5, 2021Date of Patent: June 28, 2022Assignee: KIOXIA CORPORATIONInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 11362106Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: January 5, 2021Date of Patent: June 14, 2022Assignee: KIOXIA CORPORATIONInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20220139955Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Applicant: Kioxia CorporationInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Junya MATSUNAMI, Tomoko FUJIWARA, Hideaki AOCHI, Ryouhei KIRISAWA, Yoshimasa MIKAJIRI, Shigeto OOTA
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Patent number: 11257842Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: April 15, 2020Date of Patent: February 22, 2022Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20220028892Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: October 12, 2021Publication date: January 27, 2022Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Patent number: 11195849Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.Type: GrantFiled: September 13, 2019Date of Patent: December 7, 2021Assignee: Toshiba Memory CorporationInventors: Yasuhito Yoshimizu, Yuji Setta, Masaru Kito
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Patent number: RE49152Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.Type: GrantFiled: July 10, 2020Date of Patent: July 26, 2022Assignee: Kioxia CorporationInventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota