Patents by Inventor Masaru Kuki

Masaru Kuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5287318
    Abstract: In a flash-type electrically erasable programmable read-only memory (EEPROM), the erasure block decoder provided in the row decoder outputs a signal for simultaneously driving half the erasure line drivers in the erasure line driver array, or a signal for simultaneously driving the other half of the erasure line drivers in the erasure line driver array, according to an externally applied address signal. Therefore, the erasure operation test of all the blocks corresponding one-to-one to the erasure line drivers can be completed in two erasure operations, one for each corresponding half of the memory.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: February 15, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaru Kuki, Yukio Kitaguchi
  • Patent number: 5168566
    Abstract: A computer peripheral device incorporating a multi-task control device which is extremely useful for such programs controlling the microcomputer system. In particular, the multi-task control device effectively controls a plurality of tasks executed by the CPU by using means other than the CPU including such means for controlling operations needed for comparing priority orders between a plurality of tasks, and the other means for generating interrupt operations from this control device against the CPU needed for switching tasks being executed in accordance with the result of the priority comparative operations.
    Type: Grant
    Filed: January 27, 1992
    Date of Patent: December 1, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaru Kuki, Toshimitsu Nakade, Hirotake Hayashi, Takaaki Uno
  • Patent number: 4847751
    Abstract: In a microcomputer system, having independently programmed tasks and a master control processing unit (CPU), tasks can be switched independent of the master CPU through the use of a multi-task support processor which may, for example, be connected to the microcomputer system via an input/output (I/O) port. The multi-task support processor includes a memory for storing task control programs, a data memory and task control memory, a timer, a controller for controlling multi-task operations, and a master CPU interface element. Tasks including task control commands are stored in a memory for execution by the master CPU. The master CPU, upon encountering a task control command, sends that command to the multi-task support processor which becomes activated to control the switching and communications between the tasks under the direction of the received task control command, so that tasking control may be performed independent of the master CPU.
    Type: Grant
    Filed: June 8, 1987
    Date of Patent: July 11, 1989
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshimitsu Nakade, Masaru Kuki, Takaaki Uno