Patents by Inventor Masaru Matsumura
Masaru Matsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6381680Abstract: A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.Type: GrantFiled: June 1, 1998Date of Patent: April 30, 2002Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Masaru Matsumura
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Data processing system which controls operation of cache memory based and the address being accessed
Patent number: 5822761Abstract: A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.Type: GrantFiled: February 6, 1997Date of Patent: October 13, 1998Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Masaru Matsumura -
Patent number: 5619677Abstract: A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.Type: GrantFiled: May 17, 1996Date of Patent: April 8, 1997Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Masaru Matsumura
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Patent number: 5509133Abstract: A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.Type: GrantFiled: May 5, 1995Date of Patent: April 16, 1996Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Masaru Matsumura
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Patent number: 5502825Abstract: A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.Type: GrantFiled: March 29, 1995Date of Patent: March 26, 1996Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Masaru Matsumura
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Patent number: 5479625Abstract: A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status register in the above-mentioned microcomputer system), which is accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) which is accessible by the central processing system is performed. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address does not correspond to that area accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.Type: GrantFiled: December 11, 1991Date of Patent: December 26, 1995Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Masaru Matsumura
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Patent number: 5148526Abstract: A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status register in the above-mentioned microcomputer system) which is accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) which is accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address does not correspond to the area accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.Type: GrantFiled: April 8, 1988Date of Patent: September 15, 1992Assignees: Hitachi Ltd., Hitachi Micro Computer Engineering Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Masaru Matsumura