Patents by Inventor Masaru Morohashi
Masaru Morohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11694738Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.Type: GrantFiled: July 20, 2021Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Masaru Morohashi, Ryo Nagoshi, Yuan He, Yutaka Ito
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Patent number: 11521669Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.Type: GrantFiled: April 6, 2021Date of Patent: December 6, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Honoka Enomoto, Masaru Morohashi
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Patent number: 11322192Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.Type: GrantFiled: February 28, 2020Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventors: Masaru Morohashi, Hidekazu Noguchi
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Patent number: 11222682Abstract: Apparatuses and methods for generating refresh addresses for row hammer refresh operations are disclosed. In some examples, determination of a row address associated with a highest count value may be initiated at a precharge command preceding a row hammer refresh operation. The row address determined to be associated with the highest count value may be provided for generating the refresh addresses.Type: GrantFiled: August 31, 2020Date of Patent: January 11, 2022Assignee: Micron Technology, Inc.Inventors: Honoka Enomoto, Masaru Morohashi
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Publication number: 20210350844Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.Type: ApplicationFiled: July 20, 2021Publication date: November 11, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Masaru Morohashi, Ryo Nagoshi, Yuan He, Yutaka Ito
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Patent number: 11152050Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.Type: GrantFiled: June 19, 2018Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Masaru Morohashi, Ryo Nagoshi, Yuan He, Yutaka Ito
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Publication number: 20210225432Abstract: Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Honoka Enomoto, Masaru Morohashi
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Patent number: 11043254Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.Type: GrantFiled: March 19, 2019Date of Patent: June 22, 2021Assignee: Micron Technology, Inc.Inventors: Honoka Enomoto, Masaru Morohashi
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Patent number: 10910034Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.Type: GrantFiled: August 12, 2019Date of Patent: February 2, 2021Assignee: Micron Technology, Inc.Inventor: Masaru Morohashi
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Publication number: 20200302994Abstract: Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Honoka Enomoto, Masaru Morohashi
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Publication number: 20200202921Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.Type: ApplicationFiled: February 28, 2020Publication date: June 25, 2020Applicant: Micron Technology, Inc.Inventors: Masaru Morohashi, Hidekazu Noguchi
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Patent number: 10580475Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.Type: GrantFiled: January 22, 2018Date of Patent: March 3, 2020Assignee: Micron Technology, Inc.Inventors: Masaru Morohashi, Hidekazu Noguchi
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Publication number: 20190385667Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.Type: ApplicationFiled: June 19, 2018Publication date: December 19, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Masaru Morohashi, Ryo Nagoshi, Yuan He, Yutaka Ito
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Publication number: 20190362775Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.Type: ApplicationFiled: August 12, 2019Publication date: November 28, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Masaru Morohashi
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Patent number: 10381064Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.Type: GrantFiled: January 19, 2018Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventor: Masaru Morohashi
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Publication number: 20190237132Abstract: Disclosed herein is an apparatus that includes a memory cell array including a normal memory region assigned to first value of a redundant signal and a redundancy memory region assigned to a second value of the redundant signal; a first circuit configured to receive a row address signal, produce the first value of the redundant signal if the first circuit detects that the row address signal is inconsistent to any of redundancy information, and produce the second value of the redundant signal and additional row address signal if the first circuit detects that the row address signal is consistent to any of the redundancy information; and a second circuit configured to produce further additional row address signal based on the row address signal and the first value of the redundant signal or based on the additional row address signal and the second value of the redundant signal.Type: ApplicationFiled: January 30, 2018Publication date: August 1, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Masaru Morohashi
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Publication number: 20190228815Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.Type: ApplicationFiled: January 22, 2018Publication date: July 25, 2019Applicant: Micron Technology, Inc.Inventors: Masaru Morohashi, Hidekazu Noguchi
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Publication number: 20190228814Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include, a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.Type: ApplicationFiled: January 19, 2018Publication date: July 25, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Masaru Morohashi
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Patent number: 10360954Abstract: Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes an identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.Type: GrantFiled: November 15, 2018Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventor: Masaru Morohashi
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Publication number: 20190088296Abstract: Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes an identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.Type: ApplicationFiled: November 15, 2018Publication date: March 21, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Masaru Morohashi