Patents by Inventor Masaru Nagase

Masaru Nagase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7885720
    Abstract: The decoder includes a memory to store the jump time for a seek operation. The decoder affords frame numbers to the frames and saves in the memory the current frame number of a frame being read out. The decoder saves a frame number of a jump destination calculated on the basis of the current frame number and the jump time as read out from the memory. The decoder reverts to the header on a seek operation accepted, and affords provisional frame numbers to the frames. The decoder further decodes the compressed data from the frame following the frame the provisional frame number of which coincides with the frame number of the jump destination, in fast feed, or from the frame following the frame the provisional frame number of which coincides with a frame number by one before the frame number of jump destination, in rewind.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: February 8, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Masaru Nagase, Hirofumi Muramatsu
  • Publication number: 20070230897
    Abstract: The decoder includes a memory to store the jump time for a seek operation. The decoder affords frame numbers to the frames and saves in the memory the current frame number of a frame being read out. The decoder saves a frame number of a jump destination calculated on the basis of the current frame number and the jump time as read out from the memory. The decoder reverts to the header on a seek operation accepted, and affords provisional frame numbers to the frames. The decoder further decodes the compressed data from the frame following the frame the provisional frame number of which coincides with the frame number of the jump destination, in fast feed, or from the frame following the frame the provisional frame number of which coincides with a frame number by one before the frame number of jump destination, in rewind.
    Type: Application
    Filed: April 3, 2007
    Publication date: October 4, 2007
    Inventors: Masaru Nagase, Hirofumi Muramatsu
  • Publication number: 20070055847
    Abstract: The operational processor includes a general-purpose register that holds data associated with operation processing, and a program status register that holds information associated with the status of the operational processor. The data and information are saved during interrupt processing or task switching. The program status register holds in its bit positions C1-Cn a portion of data resulting from the operation processing. The held data are the n most significant bits of the least significant bits of the data resulting from the operation processing which are not held in the general-purpose register, and are for use in the operation. The operational processor may perform fewer operations than the double precision operation, and improve the operation precision without increasing the task switching time.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Masaru Nagase, Makoto Ohnishi