Abstract: An interlayer insulating film made of insulating material is deposited on a substrate having a conductive region at least partially on the surface area thereof. A connection hole is formed through the interlayer insulating film, to expose the conductive region. The connection hole is filled with a plug made of conductive material. An underlying layer made of Ti is deposited over the whole surface of the substrate including the surface of the plug. A wiring layer made of Al alloy is deposited on the underlying layer, without exposing the substrate to the external atmosphere after the deposition of the Ti layer. The wiring layer is reflowed by heating the substrate. A method is provided which is capable of connecting an upper wiring layer to a lower conductive region without lowering resistance to electromigration and lowering step coverage.

Abstract: A phosphor having a surface coated with a metal alkoxide containing a quaternary ammonium salt.

Abstract: A wiring layer 36A is formed by sputtering, reflowing and patterning of an Al alloy layer on insulating layers 32 and 34 covering the surface of a semiconductor substrate 30. A silicon oxide layer 38 is formed by coating a hydrogen silsesquioxane resin film flatly over the layer 36A and by successive heat treatment. Then a silicon oxide layer 40 is formed on the layer 38 by plasma-enhanced chemical vapor deposition. After formation of the desired connecting hole in an interlayer insulating layer made of a lamination of the layers 38 and 40, a wiring layer 46 connected with the layer 36A via the connecting hole is formed by sputtering, reflowing and patterning of an Al alloy layer. Results of the measurements of the resistance of the via chains having 20000 vias indicated that resistace rise has not been observed. A multi-layered wiring which is highly resistant to stress migration is provided.

Abstract: A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

Abstract: A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

Abstract: After a contact hole is formed in an insulating film covering the surface of a semiconductor substrate, a Ti layer and a TiON (or TiN) layer are sequentially formed on the insulating film. On the TiON layer an Al alloy layer 18 containing Si is formed, and a reflow thermal treatment is performed after or during the formation of the Al alloy layer in order to improve step coverage. During this thermal treatment, Si nodules are generated. After a Ti layer is formed on the reflowed Al alloy layer, an annealing thermal treatment is performed for 120 seconds at a temperature of 450.degree. to 500.degree. C. With this thermal treatment, Si of Si nodules is absorbed in the Ti layer so that Si nodules are reduced or extinguished. After an antireflection TiN (or TiON) layer is formed on the Ti layer, wiring patterns are formed by using resist patterns as a mask. Since Si nodules are extinguished, wiring resistance can be reduced and an etching time can be shortened.

Abstract: After forming a contact hole in an insulator layer, which is formed on a substrate covering an impurity doped region, a Ti film, a TiN film (or TiON film), and an Al alloy (for example, an alloy of Al--Si--Cu) layer are sputtered (consecutively from the bottom level) for forming a wiring material layer. A wiring layer is formed by patterning the wiring material layer in accordance with a wiring pattern. Portions with a 0% coverage of the Al alloy layer are eliminated by sputtering the Al alloy layer with a substrate temperature in a range between 100.degree.and 150.degree. C.

Abstract: On an insulating film covering the surface of a semiconductor substrate, a lower wiring layer made of Al or Al alloy is formed. An insulating film having a contact hole is formed on the lower wiring layer and the substrate. An upper wiring layer made of Al or Al alloy is formed on the insulating film and connected to the lower wiring layer via the contact hole. In such a multilayered wiring structure, the size of Al grain of the lower wiring layer, at least at the surface just under the contact hole, is made smaller than the bottom size of the contact hole. With this setting, Al atoms are supplied sufficiently from the lower wiring layer to the interface between the lower and upper wiring layers, preventing wiring disconnection caused by the peeling off of the interface.

Abstract: In a multi-layer wiring structure of an integrated circuit device, occurrence of voids due to electromigration in the vicinity of an interface between upper and lower wiring layers is suppressed. The interface is cleaned in vacuum and grain size of the wiring layers is controlled. After an interlayer insulating film (16) having a connection hole (16A) is formed to cover a first wiring layer (14) of Al or an Al alloy, a second wiring layer (18) of Al or an Al alloy is formed and connected to the first wiring layer through the connection hole. When the second wiring layer is formed, grains (G.sub.2) of the second wiring layer are formed so as to be :respectively continuously adjacent to and substantially equal in size to grains (G.sub.1) of the first wiring layer which appear at the interface.

Abstract: The object of the present invention is to provide a color picture tube, which has a fluorescent film of a red emission component exhibiting a red emission with a deep color tone and is excellent in emission brightness. This object can effectively be accomplished by a color picture tube, having a face plate on which dot-shaped or stripe-shaped fluorescent films of blue, green and red emission components are respectively formed, characterized in that the fluorescent film of the red emission component is formed of a red emission composition comprising a mixture of an europium activated rare earth element oxide phosphor having an x value of 0.630 to 0.652 in CIE Chromaticity Representation and an europium activated rare earth element oxysulfide phosphor having an x value of 0.652 to 0.674 in CIE Chromaticity Representation, the red composition having an x of 0.647 to 0.662 in CIE Chromaticity Representation.

Abstract: A color cathode-ray tube having a fluorescent screen of red-, blue- and green-emitting phosphors as image elements of a fluorescent layer, wherein at least one of said phosphors is coated with a double oxide of zinc and aluminum.

Abstract: A color cathode-ray tube having a fluorescent screen of red-, blue- and green-emitting phosphors as image elements of a fluorescent layer, wherein at least one of said phosphors is coated with a double oxide of zinc and aluminum.