Patents by Inventor Masaru Nukiwa
Masaru Nukiwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6875638Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: GrantFiled: March 19, 2002Date of Patent: April 5, 2005Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Publication number: 20040053444Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: ApplicationFiled: August 29, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Patent number: 6693029Abstract: A method for manufacturing a substrate, including adhering an adhesive layer to an organic insulation substrate to form a first part; forming a via hole in the first part such that the via hole penetrates the first part; forming a conductive metal film so that the conductive metal film covers the via-hole on one side of the first part; using an electrolytic plating process, where the conductive metal Film is used as an electrode, to form a metal via member within the via hole and to form an inter-layer wire; and removing an entirety of the conductive metal film without removing the inter-layer formed by the electrolytic plating process; repeating steps (a)-(e) for a second part; and thereafter attaching the first part to the second part.Type: GrantFiled: December 28, 2001Date of Patent: February 17, 2004Assignee: Fujitsu LimitedInventors: Makoto Iijima, Masaru Nukiwa, Seiji Ueno, Muneharu Morioka
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Publication number: 20030087483Abstract: A semiconductor device includes a multi-flexible substrate and semiconductor chips mounted thereon. The multi-flexible substrate is configured such that organic insulation substrate layers and filmy adhesive layers are alternatively stacked together and wiring layers formed therein are interconnected by means of vias. Each of the vias consisting of a via-hole which is formed penetrating both the organic insulation substrate layers and the filmy adhesive layers and a metal via member 26 which is provided in the via-hole and made of an identical material. A method of manufacturing the multi-flexible substrate for the semiconductor device is also disclosed.Type: ApplicationFiled: December 28, 2001Publication date: May 8, 2003Applicant: FUJITSU LIMITEDInventors: Makoto Iijima, Masaru Nukiwa, Seiji Ueno, Muneharu Morioka
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Publication number: 20030082846Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: ApplicationFiled: March 19, 2002Publication date: May 1, 2003Applicant: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Patent number: 6396155Abstract: A semiconductor device includes a semiconductor element on which a plurality of bumps are formed and a substrate having a first surface on which a plurality of protruding electrodes are protrudingly formed in correspondence to an arrangement of the bumps, and a second surface on which balls serving as mounting terminals are formed. The semiconductor element is bonded in a face-down manner to the substrate with the protruding electrodes being embedded into the bumps. Alloy layers having materials identical to those of the bumps and the protruding electrodes are formed on interfaces of the bumps and the protruding electrodes.Type: GrantFiled: June 27, 2000Date of Patent: May 28, 2002Assignee: Fujitsu LimitedInventors: Masaru Nukiwa, Makoto Iijima, Seiji Ueno, Muneharu Morioka
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Patent number: 6351031Abstract: A semiconductor device includes a multi-flexible substrate and semiconductor chips mounted thereon. The multi-flexible substrate is configured such that organic insulation substrate layers and filmy adhesive layers are alternatively stacked together and wiring layers formed therein are interconnected by means of vias. Each of the vias consisting of a via-hole which is formed penetrating both the organic insulation substrate layers and the filmy adhesive layers and a metal via member 26 which is provided in the via-hole and made of an identical material. A method of manufacturing the multi-flexible substrate for the semiconductor device is also disclosed.Type: GrantFiled: March 22, 2000Date of Patent: February 26, 2002Assignee: Fujitsu LimitedInventors: Makoto Iijima, Masaru Nukiwa, Seiji Ueno, Muneharu Morioka
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Patent number: 6347037Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.Type: GrantFiled: November 4, 1998Date of Patent: February 12, 2002Assignee: Fujitsu LimitedInventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi, Masaru Nukiwa, Takao Akai
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Publication number: 20020001178Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.Type: ApplicationFiled: November 4, 1998Publication date: January 3, 2002Inventors: MAKOTO IIJIMA, TETSUSHI WAKABAYASHI, TOSHIO HAMANO, MASAHARU MINAMIZAWA, MASASHI TAKENAKA, TATUROU YAMASHITA, MASATAKA MIZUKOSHI, MASARU NUKIWA, TAKAO AKAI
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Patent number: 5923540Abstract: A semiconductor device has an electrical circuit and a grounding terminal. A multilayer substrate has a plurality of insulator layers and conductor layers in a stacked arrangement and a surface with first and second regions, the conductor layers making electrical contact with the electrical circuit and the grounding terminal of the semiconductor device. The first region generally surrounds the semiconductor device and has first connecting conductors penetrating at least a part of the multilayer substrate so that each of the first conductors makes contact with one or a plurality of corresponding conductor layers. The second region generally surrounds the first region and has second connecting conductors penetrating at least a part of the multilayer substrate and only making contact with one or a plurality of conductor layers coupled to the grounding terminal of the semiconductor device.Type: GrantFiled: June 12, 1997Date of Patent: July 13, 1999Assignee: Fujitsu LimitedInventors: Kenji Asada, Toshio Hamano, Masaru Nukiwa