Patents by Inventor Masaru Numano

Masaru Numano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8582260
    Abstract: According to one embodiment, an integrated circuit includes a first external terminal, a second external terminal, a third external terminal grounded, an output transistor connected to the second and third external terminals, an ESD protection circuit connected between the second external terminal and the third external terminal, a diode connected between the first and second external terminals, a power supply circuit connected between the first and third external terminals, an internal circuit connected between the power supply circuit and the third external terminal, a current source circuit, and a drive circuit having a first and second input terminals and an output terminal connected to the control electrode of the output transistor. When a voltage larger than a maximum rating voltage is applied to the second external terminal, the drive circuit turns off the output transistor and the ESD protection circuit operates.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Shimomura, Masaru Numano
  • Patent number: 8547670
    Abstract: According to one embodiment, an integrated circuit includes a power supply terminal, an output terminal, a high side output transistor including a first electrode connected to the power supply terminal, a second electrode connected to the output terminal, and a control electrode, a transistor which is connected between the control electrode and the second electrode of the high side output transistor and which short-circuits the control electrode and the second electrode in an on state, a trigger circuit connected between the power supply terminal and the control electrode of the transistor, and an Electro Static Discharge (ESD) protection circuit connected between the power supply terminal and the output terminal. When a voltage larger than a maximum rating voltage is applied to the power supply terminal, the trigger circuit operates, the transistor turns on, the high side output transistor turns off, and the ESD protection circuit operates.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Shimomura, Masaru Numano
  • Patent number: 8427798
    Abstract: In one embodiment, a semiconductor integrated circuit includes a power source circuit connected to a terminal of a first high potential side power source and outputs a voltage of a second high potential side power source, and an output transistor outputting an output signal to an output terminal. A cathode of a first diode is connected to the terminal of the first high potential side power source and an anode thereof is connected to the output terminal. A current source and a capacitor are connected between a terminal of the second high potential side power source and the terminal of a low potential side power source. A signal from a connection node of the current source and the capacitor and a control signal are inputted to a logic circuit, and the logic circuit outputs a signal obtained by a logic operation to the control terminal of the output transistor.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Shimomura, Masaru Numano
  • Patent number: 8405429
    Abstract: According to one embodiment, a power supply voltage monitor circuit includes a constant voltage circuit, a level shift circuit, a clamping circuit, a first differential circuit, and a second differential circuit. The first differential circuit include a differential unit receiving a constant current supplied from a current source and outputting an output voltage in accordance with a potential difference between a first input voltage obtained by subjecting the second constant voltage to resistive division and a second input voltage obtained by subjecting the power supply voltage to resistive division, and an output unit outputting a rectangular signal in accordance with the output voltage of the differential unit.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Numano
  • Publication number: 20120212869
    Abstract: According to one embodiment, an integrated circuit includes a first external terminal, a second external terminal, a third external terminal grounded, an output transistor connected to the second and third external terminals, an ESD protection circuit connected between the second external terminal and the third external terminal, a diode connected between the first and second external terminals, a power supply circuit connected between the first and third external terminals, an internal circuit connected between the power supply circuit and the third external terminal, a current source circuit, and a drive circuit having a first and second input terminals and an output terminal connected to the control electrode of the output transistor. When a voltage larger than a maximum rating voltage is applied to the second external terminal, the drive circuit turns off the output transistor and the ESD protection circuit operates.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 23, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi SHIMOMURA, Masaru Numano
  • Publication number: 20120212868
    Abstract: According to one embodiment, an integrated circuit includes a power supply terminal, an output terminal, a high side output transistor including a first electrode connected to the power supply terminal, a second electrode connected to the output terminal, and a control electrode, a transistor which is connected between the control electrode and the second electrode of the high side output transistor and which short-circuits the control electrode and the second electrode in an on state, a trigger circuit connected between the power supply terminal and the control electrode of the transistor, and an Electro Static Discharge (ESD) protection circuit connected between the power supply terminal and the output terminal. When a voltage larger than a maximum rating voltage is applied to the power supply terminal, the trigger circuit operates, the transistor turns on, the high side output transistor turns off, and the ESD protection circuit operates.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 23, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi SHIMOMURA, Masaru Numano
  • Publication number: 20110316619
    Abstract: According to one embodiment, a power supply voltage monitor circuit includes a constant voltage circuit, a level shift circuit, a clamping circuit, a first differential circuit, and a second differential circuit. The first differential circuit include a differential unit receiving a constant current supplied from a current source and outputting an output voltage in accordance with a potential difference between a first input voltage obtained by subjecting the second constant voltage to resistive division and a second input voltage obtained by subjecting the power supply voltage to resistive division, and an output unit outputting a rectangular signal in accordance with the output voltage of the differential unit.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 29, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masaru Numano
  • Publication number: 20110255201
    Abstract: In one embodiment, a semiconductor integrated circuit includes a power source circuit connected to a terminal of a first high potential side power source and outputs a voltage of a second high potential side power source, and an output transistor outputting an output signal to an output terminal. A cathode of a first diode is connected to the terminal of the first high potential side power source and an anode thereof is connected to the output terminal. A current source and a capacitor are connected between a terminal of the second high potential side power source and the terminal of a low potential side power source. A signal from a connection node of the current source and the capacitor and a control signal are inputted to a logic circuit, and the logic circuit outputs a signal obtained by a logic operation to the control terminal of the output transistor.
    Type: Application
    Filed: February 24, 2011
    Publication date: October 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi SHIMOMURA, Masaru Numano
  • Patent number: 7642494
    Abstract: A light emitting apparatus includes: a light emitting device with one terminal connected to a power supply terminal; a voltage detector connected between the power supply terminal and a ground terminal; a driver circuit unit connected between an input terminal receiving a signal as input and the ground terminal; a first switch connected between another terminal of the light emitting device and the driver circuit unit; a second switch connected between the input terminal and the other terminal of the light emitting device; and a switch controller.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: January 5, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Numano
  • Publication number: 20090085542
    Abstract: An output signal from a driver is provided to an output unit which includes first and second transistors to output a drive signal for driving a power device. A control signal is supplied from a control signal supply. The control signal indicates an enabled state and a disabled state to control the first and second transistors. The control signal is provided to a voltage output circuit. An output signal from the voltage output circuit is provided to a voltage hold circuit. The first and second transistors are turned off by a disable circuit when the control signal is in the disabled state. A shutdown circuit operates to draw out current from an output terminal of the output unit based on a signal provided from the voltage hold circuit and the control signal when the control signal is in the disabled state.
    Type: Application
    Filed: September 24, 2008
    Publication date: April 2, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Numano, Shigeyuki Sakura, Yasuzumi Hirao
  • Patent number: 7499298
    Abstract: A semiconductor integrated circuit includes: a power supply circuit; a voltage-current conversion circuit connected with an output of the power supply circuit, the voltage-current conversion circuit having an output terminal; a current-voltage conversion circuit connected with the output terminal of the voltage-current conversion circuit, the current-voltage conversion circuit having an output terminal; a constant-voltage line connected with the output terminal of the current-voltage conversion circuit; an output circuit which has an output terminal to which an external element is connected at a rear stage thereof; and a protection circuit which receives a potential of the constant-voltage line and the output signal from the power supply circuit to control a potential of the output terminal, and prevents the external element from operating when an increase in the potential of the constant-voltage line is insufficient or the power supply voltage is not in a steady state.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: March 3, 2009
    Assignee: Kabushik Kaisha Toshiba
    Inventors: Yasuzumi Hirao, Masaru Numano
  • Publication number: 20080265185
    Abstract: A light emitting apparatus includes: a light emitting device with one terminal connected to a power supply terminal; a voltage detector connected between the power supply terminal and a ground terminal; a driver circuit unit connected between an input terminal receiving a signal as input and the ground terminal; a first switch connected between another terminal of the light emitting device and the driver circuit unit; a second switch connected between the input terminal and the other terminal of the light emitting device; and a switch controller.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 30, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masaru Numano
  • Patent number: 7304594
    Abstract: According to one aspect of this invention, there is provided a transmitting and receiving device including a transmitting device having a pulse width modulation encoder which generates a pulse width signal having a pulse width corresponding to the binary digital signals outputted from the plurality of sigma-delta analog-to-digital conversion units, and a light-emitting element drive unit which generates and transmits an optical signal by causing a light-emitting element to emit light on the basis of the pulse width signal, and a receiving device having an optical reception unit which converts a current signal, obtained by receiving the optical signal by a light-receiving element, into the pulse width signal, and a pulse width demodulation decoder which reconstructs the binary digital signals of a plurality of channels on the basis of the pulse width signal.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: December 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeyuki Sakura, Hiroshi Suzunaga, Masaru Numano, Atsushi Iwata, Yoshitaka Murasaka, Toshifumi Imamura
  • Publication number: 20070075886
    Abstract: According to one aspect of this invention, there is provided a transmitting and receiving device including a transmitting device having a pulse width modulation encoder which generates a pulse width signal having a pulse width corresponding to the binary digital signals outputted from the plurality of sigma-delta analog-to-digital conversion units, and a light-emitting element drive unit which generates and transmits an optical signal by causing a light-emitting element to emit light on the basis of the pulse width signal, and a receiving device having an optical reception unit which converts a current signal, obtained by receiving the optical signal by a light-receiving element, into the pulse width signal, and a pulse width demodulation decoder which reconstructs the binary digital signals of a plurality of channels on the basis of the pulse width signal.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 5, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeyuki Sakura, Hiroshi Suzunaga, Masaru Numano, Atsushi Iwata, Yoshitaka Murasaka, Toshifumi Imamura
  • Publication number: 20060273801
    Abstract: A semiconductor integrated circuit includes: a power supply circuit; a voltage-current conversion circuit connected with an output of the power supply circuit, the voltage-current conversion circuit having an output terminal; a current-voltage conversion circuit connected with the output terminal of the voltage-current conversion circuit, the current-voltage conversion circuit having an output terminal; a constant-voltage line connected with the output terminal of the current-voltage conversion circuit; an output circuit which has an output terminal to which an external element is connected at a rear stage thereof; and a protection circuit which receives a potential of the constant-voltage line and the output signal from the power supply circuit to control a potential of the output terminal, and prevents the external element from operating when an increase in the potential of the constant-voltage line is insufficient or the power supply voltage is not in a steady state.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 7, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuzumi Hirao, Masaru Numano
  • Patent number: 7075956
    Abstract: An optical semiconductor device comprises: an optical semiconductor element; and a circuit. The circuit is connected to the optical semiconductor element and has a series rectifying circuit including a plurality of zener diodes connected in series. The circuit further has a rectifying element whose anode is connected to an anode of the series rectifying circuit.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: July 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Numano
  • Patent number: 6906573
    Abstract: A semiconductor circuit disclosed herein includes a first output MOS transistor which includes a first terminal connected to a first power source and a second terminal connected to an output terminal to be connected to a load circuit; a second output MOS transistor which includes a third terminal connected to a second power source and a fourth terminal connected to the output terminal; a first functional block circuit which is connected between a control terminal of one of the first output MOS transistor and the second output MOS transistor and the output terminal, wherein the first functional block circuit includes at least one first diode, the first diode being a CB shorted NPN transistor or a CB shorted LPNP transistor; and a second functional block circuit which is provided in parallel with the first functional block circuit and includes at least one second diode connected in an opposite direction to the first diode of the first functional block circuit, the second diode being a CB shorted NPN transistor
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 14, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Numano
  • Publication number: 20040151219
    Abstract: An optical semiconductor device comprises: an optical semiconductor element; and a circuit. The circuit is connected to the optical semiconductor element and has a series rectifying circuit including a plurality of zener diodes connected in series. The circuit further has a rectifying element whose anode is connected to an anode of the series rectifying circuit.
    Type: Application
    Filed: August 27, 2003
    Publication date: August 5, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masaru Numano
  • Publication number: 20030197992
    Abstract: A semiconductor circuit disclosed herein includes a first output MOS transistor which includes a first terminal connected to a first power source and a second terminal connected to an output terminal to be connected to a load circuit; a second output MOS transistor which includes a third terminal connected to a second power source and a fourth terminal connected to the output terminal; a first functional block circuit which is connected between a control terminal of one of the first output MOS transistor and the second output MOS transistor and the output terminal, wherein the first functional block circuit includes at least one first diode, the first diode being a CB shorted NPN transistor or a CB shorted LPNP transistor; and a second functional block circuit which is provided in parallel with the first functional block circuit and includes at least one second diode connected in an opposite direction to the first diode of the first functional block circuit, the second diode being a CB shorted NPN transistor
    Type: Application
    Filed: March 31, 2003
    Publication date: October 23, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Masaru Numano