Patents by Inventor Masaru Okazoe

Masaru Okazoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4004159
    Abstract: A semiconductor memory device comprising a composite structure of semiconductor-insulation layer-floating gate-insulation layer-control gate, in which a periphery of said floating gate is formed to extend up to and immediately above at least one of source and drain regions, such that both overlap each other through the insulation layer therebetween of silicon dioxide and of a thickness of 200 to 400A for more than 0.35 microns in length but not exceeding two times the distance between the source and drain regions.
    Type: Grant
    Filed: November 3, 1975
    Date of Patent: January 18, 1977
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuki Rai, Terutoshi Sasami, Yuzuru Hasegawa, Masaru Okazoe