Patents by Inventor Masaru Saitou

Masaru Saitou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080086873
    Abstract: A method of mounting an electronic part includes, providing a liquid at a surface of the electronic part or a suction end of a suction nozzle, attaching the electronic part to a suction end of a suction nozzle via the liquid, suctioning the liquid from the suction end to hold the electronic part at the suction end, and mounting the electronic part onto a substrate. And an apparatus for mounting an electronic part includes a liquid supplier which provides a liquid on a surface of the electronic part, and a suction nozzle which suctions the liquid and holds the electronic part in which the suction nozzle mounts the electronic part onto a substrate.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 17, 2008
    Inventors: Masaru Saitou, Takeshi Mizuno
  • Publication number: 20070102490
    Abstract: A through hole 2 in a circuit board 1 and to be joined to a lead 5 in a surface mounting component 6 is prepared from a material such as nickel, and palladium having a thermal conductivity equal to or less than 100 W/m.K, the circuit board 1 involving a alloy layer composed of at least a member selected from elements of solder 8, a pad 7, and the lead 5 in a solder joined site of the lead 5 and the pad 7, whereby a quantity of heat transmitted to the joined site via the through hole 2 is reduced at the time when wave-soldering is applied to the back of the circuit board 1 after the surface mounting component 6 was mounted, so that the joined site is maintained at a temperature equal to or less than a melting point of the alloy layer, and hence, exfoliation in an interface of the joined site is prevented, and reliability in the joint of the lead 5 and the pad 7 is elevated.
    Type: Application
    Filed: December 19, 2006
    Publication date: May 10, 2007
    Applicant: NEC CORPORATION
    Inventors: Yuki Momokawa, Eiichi Kono, Masaru Saitou, Kazuhiko Tanabe
  • Publication number: 20040238211
    Abstract: A through hole 2 in a circuit board 1 and to be joined to a lead 5 in a surface mounting component 6 is prepared from a material such as nickel, and palladium having a thermal conductivity equal to or less than 100 W/m.K, the circuit board 1 involving a alloy layer composed of at least a member selected from elements of solder 8, a pad 7, and the lead 5 in a solder joined site of the lead 5 and the pad 7, whereby a quantity of heat transmitted to the joined site via the through hole 2 is reduced at the time when wave-soldering is applied to the back of the circuit board 1 after the surface mounting component 6 was mounted, so that the joined site is maintained at a temperature equal to or less than a melting point of the alloy layer, and hence, exfoliation in an interface of the joined site is prevented, and reliability in the joint of the lead 5 and the pad 7 is elevated.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 2, 2004
    Inventors: Yuki Momokawa, Eiichi Kono, Masaru Saitou, Kazuhiko Tanabe
  • Patent number: 6558983
    Abstract: A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: May 6, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaru Saitou, Gen Tada, Akio Kitamura
  • Publication number: 20020003288
    Abstract: A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.
    Type: Application
    Filed: August 16, 2001
    Publication date: January 10, 2002
    Applicant: Fuji Electric, Co., Ltd.
    Inventors: Masaru Saitou, Gen Tada, Akio Kitamura
  • Patent number: 6316794
    Abstract: A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: November 13, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaru Saitou, Gen Tada, Akio Kitamura