Abstract: A natural invasion promoting method that is environmentally friendly, easy to carry out, can cope with a wide range of areas and inclined surfaces, achieves efficient natural invasion, and can satisfactorily promote greening on a soil surface of interest, and a spraying material used in the method are provided. A natural invasion promoting method including: spraying a spraying material containing live algae on a soil surface; breeding the live algae; and also directly or indirectly catching flying seeds or spores by a tacky substance secreted on surfaces of the live algae or a catching structure composed of the live algae to promote greening on the soil surface.

Abstract: An information protection device includes a reception unit that receives an image of a screen displayed on a terminal connected to a certain network; an extraction unit that extracts input information for the screen from the image; a determination unit that determines whether or not the input information matches predetermined information; and a control unit that performs, when the input information is determined to be matched with the predetermined information, a control for preventing the input information from being transmitted from the network.

Abstract: A caution-needed IP address estimation device includes: acquisition means for acquiring, based on a degree of exposure of a subject covered by mass media, an IP address that is associated with the subject, the IP address serving as a caution-needed IP address; and transmission means for transmitting the caution-needed IP address to a NW monitoring information database device.

Abstract: A diagnostic system for finding failures in an integrated circuit includes a scan-chain circuit which is comprised of a plurality of flip-flop circuits electrically connected in series to one another and outputs logic data stored in the flip-flop circuits on receipt of a control signal. The diagnostic system includes (a) a first identifier which identifies a circuit group which is suspected to have failure therein, among circuit groups surrounded by the scan-chain circuit, (b) a first extractor which extracts logic data of an input terminal of the circuit group having been identified by the first identifier, (c) a second extractor which extracts logic data to be input into each of fundamental logic circuits constituting the circuit group, and (d) a second identifier which identifies a fundamental logic circuit suspected to have failure therein by comparing the logic data having been extracted by the second extractor, to one another.

Abstract: A wafer testing apparatus for testing or burn-in testing a large number of LSIs formed on a wafer to be tested in a lump according to the present invention includes a base for placing the wafer to be tested; a film having a metal pattern for covering and connecting the wafer to be tested; a depressing means for contacting the metal pattern on the film to an optional electrode portion on the surface of the wafer to be tested, and depressing and fixing the film on the wafer to be tested; and a conducting means, which is a terminal on the base for conducting wirings on the wafer to be tested to wirings on the film.

Abstract: A diagnostic system for finding failures in an integrated circuit includes a scan-chain circuit which is comprised of a plurality of flip-flop circuits electrically connected in series to one another and outputs logic data stored in the flip-flop circuits on receipt of a control signal. The diagnostic system includes (a) a first identifier which identifies a circuit group which is suspected to have failure therein, among circuit groups surrounded by the scan-chain circuit, (b) a first extractor which extracts logic data of an input terminal of the circuit group having been identified by the first identifier, (c) a second extractor which extracts logic data to be input into each of fundamental logic circuits constituting the circuit group, and (d) a second identifier which identifies a fundamental logic circuit suspected to have failure therein by comparing the logic data having been extracted by the second extractor, to one another.

Abstract: The method for processing formation and sale of merchandise by means of a network according to the present invention includes an appeal for public subscription step for listening to the requests of an indefinite number of users via a network in the planning stage of the merchandise, a request collection step for forming groups of subscribers for the plan based on the requests, a classification step for classifying the images and features of the merchandise based on information collected in the request collection step, an image disclosure step for disclosing the images and the features of the merchandise via the network for each group, an agreement decision step for deciding agreement on various matters including the prices of the merchandise between the maker and the subscribers after the image disclosure step, a manufacture or formation step for manufacture or formation of the merchandise when an agreement is reached following the agreement decision, a progress status disclosure step for successively disclos

Abstract: A performer collecting company releases collection of performers in a promotion video through the Internet. Information viewers view collecting information provided by the performer collecting company on information terminals. Applicants transmit information based on the collecting information from the information terminals to the performer collecting company through the Internet. The performer collecting company selects a performer from the applicants based on the received information. The image of the selected performer is used to produce a promotion video by replacing part of an original promotion video in which a performer appears by the image of the selected performer.

Abstract: By the irradiation of a laser beam in an arbitrary cycle, as well as operating a coefficient obtained by Fourier transform of a power supply current waveform (IDDQ) obtained at the irradiation of no laser and a coefficient obtained by Fourier transform of a waveform (IDDQ+Iph) obtained by superposing a power supply current waveform obtained at the irradiation of laser and photoelectric current waveform Iph to display and compare the coefficients in a graph, existence/nonexistence of Iph can be detected. In addition, simultaneous irradiation of a plurality of positions of PN junctions of an LSI with a laser beam in different cycles enables simultaneous determination of a plurality of positions.

Abstract: An internal-logic inspection circuit in an LSI includes a MOSFET having a first diffused region connected to an internal node of an internal circuit, a second diffused region connected to a diode and a gate connected to a pad. The diode is irradiated with a laser beam while the gate of MOSFET is applied with a gate voltage, and a resultant current is measured for judging the level of the internal node. The diode can be disposed in a space where overlying interconnects are not disposed.

Abstract: A method of locating faults occurred in an LSI (Large Scale Integrated Circuit) is disclosed. Block-by-block logic information each varying in accordance with a test vector are output by dump processing using logic simulation on the basis of circuit connection information. The block-by-block logic information varying in accordance with the test vector are combined with Iddq information showing whether or not an Iddq error has occurred test vector by test vector. These information are used to execute calculation with each block on a test vector basis. As a result, a block involving a fault is detected. Subsequently, a fault is located in the fault block on a transistor basis by use of logic information showing whether or not the Iddq error is present in the block.

Abstract: A semiconductor integrated circuit having a logic verification structure includes a logic circuit formed by CMOS structure on a semiconductor substrate, in which the semiconductor integrated circuit has an impurity region irradiated by a laser beam from a back of the semiconductor substrate, for testing the logic circuit, achieving a simple logic analysis.

Abstract: A semiconductor device manufacturing process diagnosis system including a visual inspection device for detecting a physically abnormal part of a semiconductor device to be diagnosed, an LSI tester for measuring electrical characteristics of a semiconductor device and a diagnosis device and characterized in that the diagnosis device extracts, from among circuit blocks constituting a semiconductor device, a block contained in a predetermined region covering a physically abnormal part, determines whether an extracted block and an abnormal block causing abnormality of electrical characteristics are the same, with respect to a block discriminated as an abnormal block, detects a position causing abnormality of electrical characteristics within the block, and depending on whether a detected position substantially coincides with a physically abnormal part, determines whether abnormality of electrical characteristics derives from physical abnormality.

Abstract: According to the invention, the temperature and flow rate of cooling water for removing the heat of absorption are controlled artificially according to the cold output of load water by utilizing heated cooling water after the removal of the heat of absorption or heat source water, etc. According to the invention, a coolant tank and a load heat exchanger unit are provided as separate units. A load carrier is provided for cooling the load while partly evaporating the coolant through heat exchange between liquid coolant supplied from the coolant supplied from the coolant tank through a pump and the load. Mixture fluid of liquid coolant and vapor coolant after the heat exchange in the load cooler are returned to the coolant tank for separation of gas and liquid. Because the coolant tank and the load cooler are provided separately, the heat exchange with the load is performed by utilizing the latent heat of evaporation of coolant independently of possible temperature variations in the coolant tank.

Abstract: A failure point identifying method applicable to various defects and capable of promptly identifying a defect point. An LSI tester 4 sequentially impresses test vectors stored in a test vector file 1 across input terminals of a loaded LSI 5 to measure an Iddq value. A test vector number of a test vector which produced an abnormal Iddq value is delivered to a faulty block extractor 2. The faulty block extractor 2 performs logic simulation to find the input logic of each block of the LSI 5 when each test vector stored in the test vector file 1 is entered to the input terminals of the LSI 5. Moreover, a dump list associating each test vector number with the input logic is prepared from block to block. The faulty block is then identified based on the dump list of each block and the test vector number deliver from the LSI tester.

Abstract: In a semiconductor device, a plurality of functional test patterns are generated and transmitted to the semiconductor device, and it is determined whether or not an abnormal current, flows through the semiconductor device. Also, the semiconductor device is irradiated with electrons, and secondary electrons from the semiconductor device are detected. Potential contrast images are calculated in accordance with the detected secondary electrons in response to the functional test patterns. A logic operation is performed upon the potential contrast images to estimate a fault point.

Abstract: In a system for estimating a failure mode in a semiconductor device, at least one special functional test pattern is generated and transmitted to the semiconductor device. If an abnormal current is detected, V-I characteristics of the semiconductor device are detected, and are compared with reference V-I characteristics for a special failure mode, thereby estimating that the specified failure mode has occurred.

Abstract: In a semiconductor device formed by a plurality of logic blocks, plurality of functional test patterns are generated and transmitted to the semiconductor device. If an abnormal current is detected upon receipt of an i-th functional test pattern, and an output data is different from an expected data upon receipt of a j-th functional test pattern, a fault block is determined in accordance with the i-th functional test pattern and the j-th functional test pattern.

Abstract: In a semiconductor device formed by a plurality of logic blocks, a plurality of functional test patterns are generated and transmitted to the semiconductor device, and it is determined whether an abnormal current flows through the semiconductor device. When an abnormal current is detected, a fault block is determined in accordance with a table for storing the functional test patterns and the logic blocks operated by the functional test patterns.

Abstract: This invention seeks to provide an adsorption type air cooler, which has high COP and is capable of stable operation for long time. In the prior art, when vapor coolant produced through heat exchange with load water in a coolant tank functioning as an evaporator is adsorbed in an adsorbent heat exchanger, cooling water for removing the heat of adsorption is circulated at a constant temperature and a constant flow rate determined by normal environment.According to the invention as claimed in claim 1, the temperature and flow rate of cooling water for removing the heat of adsorption are controlled artificially according to the cold output of load water by utilizing heated cooling water after the removal of the heat of adsorption or heat source water, etc.According to the invention as claimed in claim 1, a coolant tank and a load heat exchanger unit are provided as separate units.