Abstract: A semiconductor device for measuring a voltage of a battery cell, including first and second nodes, and first and second battery voltage measurement units. The first node is configured to receive a first voltage, the first voltage being a voltage of a capacitor that accumulates an electric charge based on the voltage of the battery cell. The first battery voltage measurement unit measures the first voltage through a first path. The second node is configured to receive a second voltage based on the voltage of the battery cell, the second node being different from the first node. The second battery voltage measurement unit measures the second voltage through a second path that is different from the first path.

Abstract: A semiconductor device is performed a cell voltage measurement control for measuring each cell voltage of each target battery cell among a plurality of battery cells connected in series, using a difference voltage output circuit having first and second input terminals. In the measurement control, first and second connection states are formed with respect to each target battery cell so that each cell voltage is sequentially measured. Anode and cathode of each target battery cell are connected to the first and second input terminals in the first connection state, respectively, and the anode and cathode are connected to the second and first input terminal in a second connection state, respectively. Among the first and second connection states, a connection state that is first formed for a current target battery cell is the same as a connection state that has been last formed for a previous target battery cell.

Abstract: A semiconductor device for measuring a voltage of a battery cell, including first and second nodes, and first and second battery voltage measurement units. The first node is configured to receive a first voltage, the first voltage being a voltage of a capacitor that accumulates an electric charge based on the voltage of the battery cell. The first battery voltage measurement unit measures the first voltage through a first path. The second node is configured to receive a second voltage based on the voltage of the battery cell, the second node being different from the first node. The second battery voltage measurement unit measures the second voltage through a second path that is different from the first path.

Abstract: A semiconductor device is performed a cell voltage measurement control for measuring each cell voltage of each target battery cell among a plurality of battery cells connected in series, using a difference voltage output circuit having first and second input terminals. In the measurement control, first and second connection states are formed with respect to each target battery cell so that each cell voltage is sequentially measured. Anode and cathode of each target battery cell are connected to the first and second input terminals in the first connection state, respectively, and the anode and cathode are connected to the second and first input terminal in a second connection state, respectively. Among the first and second connection states, a connection state that is first formed for a current target battery cell is the same as a connection state that has been last formed for a previous target battery cell.

Abstract: A battery monitoring system including: plural battery cell sets; and semiconductor devices, wherein: each of the semiconductor devices includes a measuring section, a high side communication section that is supplied with a drive voltage in a first voltage range, and, when a semiconductor device is present at a higher position that operates at a higher operating voltage than the operating voltage of the semiconductor device itself when measuring a battery cell set on the high side of the battery cell set measured by the semiconductor device itself, can perform communication with the high side semiconductor device, a low side communication section, and a communication level converter; the semiconductor device at the highest stage further includes a signal level determination section; and the first voltage range of the highest stage is set to a specific voltage range narrower than the first voltage range of another of the semiconductor devices.

Abstract: A semiconductor device for monitoring batteries or cells connected in series has a selector switch that selects one of the batteries or cells and outputs voltages obtained from its positive and negative terminals. A pair of buffer amplifiers receives these voltages at high-impedance input terminals and output corresponding voltages to a level shifter. The level shifter generates an output voltage equal to the difference between the outputs of the buffer amplifiers. By preventing current flow between the selector switch and the level shifter, the buffer amplifiers reduce the output droop that occurs at the beginning of a voltage measurement, even if the semiconductor device is connected to the batteries or cells through a low-pass filter circuit with a comparatively large time constant. Measurement time is shortened accordingly.

Abstract: A battery monitoring system including: plural battery cell sets; and semiconductor devices, wherein: each of the semiconductor devices includes a measuring section, a high side communication section that is supplied with a drive voltage in a first voltage range, and, when a semiconductor device is present at a higher position that operates at a higher operating voltage than the operating voltage of the semiconductor device itself when measuring a battery cell set on the high side of the battery cell set measured by the semiconductor device itself, can perform communication with the high side semiconductor device, a low side communication section, and a communication level converter; the semiconductor device at the highest stage further includes a signal level determination section; and the first voltage range of the highest stage is set to a specific voltage range narrower than the first voltage range of another of the semiconductor devices.

Abstract: A semiconductor device for monitoring batteries or cells connected in series has a selector switch that selects one of the batteries or cells and outputs voltages obtained from its positive and negative terminals. A pair of buffer amplifiers receives these voltages at high-impedance input terminals and output corresponding voltages to a level shifter. The level shifter generates an output voltage equal to the difference between the outputs of the buffer amplifiers. By preventing current flow between the selector switch and the level shifter, the buffer amplifiers reduce the output droop that occurs at the beginning of a voltage measurement, even if the semiconductor device is connected to the batteries or cells through a low-pass filter circuit with a comparatively large time constant. Measurement time is shortened accordingly.

Abstract: A DA converter includes an IV conversion amplifier with output voltage having good linearity, to thus improve total harmonic distortion (THD) characteristics. In the DA converter, a first current path in which current flows due to differential switches being in the ON state in a differential switch section, and a second current path in which current flows due to differential switches being in the OFF state in the differential switch section are connected to the output side of the IV conversion amplifier. A first current flows in the first current path and a second current flows in the second current path. A current equal to the first current plus the second current that is of fixed current amount is drawn by an amplifier stage of the IV conversion amplifier.

Abstract: The present invention provides a DA converter that gives good linearity of output voltage of an IV conversion amplifier, and improves THD characteristics. In the DA converter, a current path x1 in which current flows due to differential switches being in the ON state in a differential switch section and a current path y1 in which current flows due to differential switches being in the OFF state in the differential switch section are connected to the output side of the IV conversion amplifier. A current Ix flows in the current path x1 and a current Iy flows in the current path y1. A current Ix+Iy of fixed current amount is drawn by an amplifier stage of the IV conversion amplifier.

Abstract: The current cell matrix includes 63 upper current cells and one lower current cell. Each of the current cells has 4 constant current transistors having the same size with respect to each other. The upper current cell outputs drain currents of all the constant current transistors when the cell is selected by the upper decoder. The lower current cell outputs drain currents of none, one or two constant current transistors in accordance with the select signal from the lower decoder. The analog output terminal combines and outputs the currents of the selected constant current cells. The current cell type digital-to-analog converter has the decreased differential linearity error and the decreased integral linearity error.

Abstract: A converter 10 selects desired unit current cells from unit current cells 16, 18, 20, 22 in accordance with an input code 102, and supplies currents from the selected cells to a load resistor 24 to generate an analog voltage Vdac. By supplying the constant current comprised of the currents from the selected cells and currents from non-selected cells to an offset adjuster circuit 26 including an adjusting resister 28 to generate an offset voltage Vos, the converter 10 can output a voltage Vout which is the sum of the analog voltage Vdac and the offset voltage Vos.

Abstract: A converter 10 selects desired unit current cells from unit current cells 16, 18, 20, 22 in accordance with an input code 102, and supplies currents from the selected cells to a load resistor 24 to generate an analog voltage Vdac. By supplying the constant current comprised of the currents from the selected cells and currents from non-selected cells to an offset adjuster circuit 26 including an adjusting resister 28 to generate an offset voltage Vos, the converter 10 can output a voltage Vout which is the sum of the analog voltage Vdac and the offset voltage Vos.

Abstract: The current cell matrix includes 63 upper current cells and one lower current cell. Each of the current cells has 4 constant current transistors having the same size with respect to each other. The upper current cell outputs drain currents of all the constant current transistors when the cell is selected by the upper decoder. The lower current cell outputs drain currents of none, one or two constant current transistors in accordance with the select signal from the lower decoder. The analog output terminal combines and outputs the currents of the selected constant current cells. The current cell type digital-to-analog converter has the decreased differential linearity error and the decreased integral linearity error.

Abstract: A D/A converter is provided which is capable of avoiding an increase in occupied areas of the D/A converter on a board and of obtaining an output characteristic being excellent in linearity, which enables achievement of the D/A converter having a small integral-linearity error (INL) and a small differential-linearity error (DNL). The reference current composite blocks are cascaded between current controlling device groups and an output switch. At least one out of reference current composite blocks divides composite reference current amounts based on a predetermined weight and outputs them.

Abstract: A D/A converter is provided which is capable of avoiding an increase in occupied areas of the D/A converter on a board and of obtaining an output characteristic being excellent in linearity, which enables achievement of the D/A converter having a small integral-linearity error (INL) and a small differential-linearity error (DNL). The reference current composite blocks are cascaded between current controlling device groups and an output switch. At least one out of reference current composite blocks divides composite reference current amounts based on a predetermined weight and outputs them.

Abstract: The feeder circuit to which the present invention pertains comprises means for regulating which serves to feed an electric current to a positive output terminal and a negative output terminal; means for feeding electric current which serves to feed an electric current to the means for regulating; means for regulator control which serves to control the electric current output from the means for regulating; a first resistance located between the negative terminal of the means for feeding electric current and the positive output terminal; and a second resistance located between the positive terminal of the means for feeding electric current and the negative output terminal.

Abstract: There is provided an electronic inductance circuit having a transistor, a first resistor, a second resistor, a capacitor and a first current source. The main current path of the transistor and the first resistor are connected in series to form a first serial circuit between an input terminal and an output terminal. The second resistor and the capacitor are connected in series to form a second serial circuit between the input and output terminals, thus forming a parallel circuit of the first and second serial circuits. The connection point between the second resistor and the capacitor is coupled to the control terminal of the transistor. The connection point is connected to the first current source for determining the operating point of the transistor.