Patents by Inventor Masaru Seto

Masaru Seto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10144081
    Abstract: The present invention provides an arc welding control system and method capable of simultaneously, sophisticatedly performing a weaving width control operation and a torch height control operation. Influence ratios (?w and ?z) of influences of a torch height deviation (?Ph) and a groove wall distance deviation (?Pd) with respect to a manipulated variable (?w) of a weaving width and a manipulated variable (?z) of a torch height are set in accordance with a groove angle (?) of a workpiece (5). A calculation unit (21) calculates the manipulated variables (?z and ?w) of actuators (13 and 14) regarding the torch height and the weaving width such that the influence ratios (?w and ?z) become large as the groove angle (?) becomes large.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 4, 2018
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Atsuhito Aoki, Masatsugu Takeichi, Masaru Seto, Yukio Ikezawa
  • Patent number: 9468987
    Abstract: The present invention provides an arc welding control system and method capable of simultaneously, sophisticatedly performing a weaving width control operation and a torch height control operation. Influence ratios (?w and ?z) of influences of a torch height deviation (?Ph) and a groove wall distance deviation (?Pd) with respect to a manipulated variable (?w) of a weaving width and a manipulated variable (?z) of a torch height are set in accordance with a groove angle (?) of a workpiece (5). A calculation unit (21) calculates the manipulated variables (?z and ?w) of actuators (13 and 14) regarding the torch height and the weaving width such that the influence ratios (?w and ?z) become large as the groove angle (?) becomes large.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: October 18, 2016
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Atsuhito Aoki, Masatsugu Takeichi, Masaru Seto, Yukio Ikezawa
  • Publication number: 20160107255
    Abstract: The present invention provides an arc welding control system and method capable of simultaneously, sophisticatedly performing a weaving width control operation and a torch height control operation. Influence ratios (?w and ?z) of influences of a torch height deviation (?Ph) and a groove wall distance deviation (?Pd) with respect to a manipulated variable (?w) of a weaving width and a manipulated variable (?z) of a torch height are set in accordance with a groove angle (?) of a workpiece (5). A calculation unit (21) calculates the manipulated variables (?z and ?w) of actuators (13 and 14) regarding the torch height and the weaving width such that the influence ratios (?w and ?z) become large as the groove angle (?) becomes large.
    Type: Application
    Filed: December 8, 2015
    Publication date: April 21, 2016
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Atsuhito AOKI, Masatsugu TAKEICHI, Masaru SETO, Yukio IKEZAWA
  • Patent number: 9296035
    Abstract: An object is to provide a lubricating-oil composition for forging molding excellent in lubricity, and a forging molding apparatus also suitable for the lubricating-oil composition of the present invention. The lubricating-oil composition for forging molding of the present invention includes at least two types of solid lubricants having different particle sizes, an extreme-pressure agent, and the balance of base oil. Also, the forging molding apparatus of the present invention includes paired molds formed of an upper mold and a lower mold interposing a forging material therebetween for molding and a lubricating-oil-composition spraying device for spraying the lubricating-oil composition for forging molding onto a surface of the molds, wherein the spraying device includes an oil-feeding tank storing the lubricating-oil composition and a supply tube for suctioning the lubricating-oil composition from the oil-feeding tank for supply to a nozzle, and the supply tube comprises a plurality of suction ports.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 29, 2016
    Assignees: MITSUBISHI HEAVY INDUSTRIES, LTD., SATO SPECIAL OIL, LTD.
    Inventors: Norihisa Horaguchi, Kosuke Ikeda, Masaru Seto, Yuusuke Sakama
  • Publication number: 20130299475
    Abstract: The present invention provides an arc welding control system and method capable of simultaneously, sophisticatedly performing a weaving width control operation and a torch height control operation. Influence ratios (?w and ?z) of influences of a torch height deviation (?Ph) and a groove wall distance deviation (?Pd) with respect to a manipulated variable (?w) of a weaving width and a manipulated variable (?z) of a torch height are set in accordance with a groove angle (?) of a workpiece (5). A calculation unit (21) calculates the manipulated variables (?z and ?w) of actuators (13 and 14) regarding the torch height and the weaving width such that the influence ratios (?w and ?z) become large as the groove angle (?) becomes large.
    Type: Application
    Filed: July 6, 2011
    Publication date: November 14, 2013
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Atsuhito Aoki, Masatsugu Takeichi, Masaru Seto, Yukio Ikezawa
  • Publication number: 20120192609
    Abstract: An object is to provide a lubricating-oil composition for forging molding excellent in lubricity, and a forging molding apparatus also suitable for the lubricating-oil composition of the present invention. The lubricating-oil composition for forging molding of the present invention includes at least two types of solid lubricants having different particle sizes, an extreme-pressure agent, and the balance of base oil. Also, the forging molding apparatus of the present invention includes paired molds formed of an upper mold and a lower mold interposing a forging material therebetween for molding and a lubricating-oil-composition spraying device for spraying the lubricating-oil composition for forging molding onto a surface of the molds, wherein the spraying device includes an oil-feeding tank storing the lubricating-oil composition and a supply tube for suctioning the lubricating-oil composition from the oil-feeding tank for supply to a nozzle, and the supply tube comprises a plurality of suction ports.
    Type: Application
    Filed: September 30, 2010
    Publication date: August 2, 2012
    Applicants: SATO SPECIAL OIL, LTD., MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Norihisa Horaguchi, Kosuke Ikeda, Masaru Seto, Yuusuke Sakama
  • Patent number: 8030171
    Abstract: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a plasma state including oxygen and silicon on an inner surface of the trench while applying no bias voltage (or a relatively low voltage), and a second step of filling the material in a plasma state including oxygen and silicon in the trench while applying a bias voltage (or a relatively high voltage).
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: October 4, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masaru Seto
  • Patent number: 7867890
    Abstract: The present invention provides a method of manufacturing a semiconductor device, which comprises steps of forming a plurality of wirings on a first insulating film formed on a semiconductor substrate so as to adjoin one another, forming a second insulating film on the first insulating film by a plasma CVD method and covering the wirings with the second insulating film in such a manner that air gaps are formed between the respective adjacent wirings, forming a third insulating film on the second insulating film by a high density plasma CVD method, and forming a fourth insulating film high in moisture resistance on the third insulating film.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: January 11, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masaru Seto
  • Patent number: 7745758
    Abstract: To provide an arc start method in a consumable electrode type arc welding method capable of firmly executing arc start and capable of executing high quality high speed welding by restraining a welding defect from being brought about therefor, at a portion of a wire projected from a welding tip, a temperature of a front end portion of the wire is made to be at a temperature higher than a temperature of a portion thereof near the welding tip. The front end portion of the wire is preheated to 300° C. or higher, preferably, 450° C. or higher. The front end portion of the wire is preheated by generating arc for preheating. The preheating arc is generated in a spot-like shape at a position near a terminal end portion of a predetermined welding line by constituting a current lower than a welding current.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: June 29, 2010
    Assignees: Central Motor Wheel Co., Ltd., Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Yukimitsu Suzuki, Ichiro Arita, Satoru Yamasumi, Masaru Seto, Takahisa Iizuka, Kazuhiko Onoue, Kunio Uchikoshi
  • Publication number: 20100075492
    Abstract: A method of fabricating a semiconductor memory having word lines and bit lines disposed on a semiconductor substrate, with memory cells being formed at intersecting portions of the word lines and the bit lines. The method includes forming a first insulating film on the semiconductor substrate, forming a first polysilicon film on the first insulating film, patterning the first polysilicon film to form floating gates of the memory cells and an etching stop layer covering and surrounding contact portions of the word lines in a plan view, forming a second insulating film on the first polysilicon film, forming a conductive film on the second insulating film, patterning the conductive film to form control gates of the memory cells and strip-shaped regions as the word lines, accumulating an interlayer insulating film on the conductive film, and etching the interlayer insulating film, and opening contact holes for the contact portions.
    Type: Application
    Filed: November 30, 2009
    Publication date: March 25, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Masaru Seto
  • Patent number: 7642595
    Abstract: There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of fabricating the nonvolatile semiconductor memory. Plural word lines and plural bit lines are disposed on a semiconductor substrate, and there are memory cells at intersecting portions of the word lines and the bit lines. At contact portions of the word lines and metal wires of an upper layer, polysilicon regions, which include the contact portions, are formed beneath a polysilicon forming the word lines, as an etching stop layer at a time of forming contacts.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: January 5, 2010
    Assignee: OKI Semiconductor Co., Ltd.
    Inventor: Masaru Seto
  • Patent number: 7625850
    Abstract: A high-temperature lubricating oil composition is provided, which is resistant to hardening and sludge formation, and displays minimal evaporation loss and superior thermal stability, even under practical high-temperature open system conditions such as those found in a tenter. A lubricating oil composition that provides excellent lubrication without damaging members used within working machinery is also provided. The lubricating oil composition comprises a polyolester based synthetic oil and a C12 to C72 fatty acid and/or a diphenylamine derivative containing an arylalkyl group with a number average molecular weight of 400 to 800.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: December 1, 2009
    Assignees: Mitsubishi Heavy Industries, Ltd., Sato Special Oil Co., Ltd.
    Inventors: Norihisa Horaguchi, Shiki Matsuo, Hideo Kometani, Naomoto Ishikawa, Tatsushi Seko, Yusuke Kinoshita, Masaru Seto, Kimihito Hitotsumatsu
  • Patent number: 7618861
    Abstract: Separate first and second floating gates for attracting carriers transferring in a transistor structure having a channel region and first and second main electrode regions into charge storage films therebelow are formed so as to largely face a control gate. The control gate between the separate first and second floating gates faces to the channel region via thin interlayer insulating layer. Therefore, a semiconductor device according to the present invention can inject electrons the charge storage film without causing writing errors in a writing operation, and therefore can increase in reliability thereof, control a writing voltage, prevent loss of the electrons stored in the charge storage film, and reliably apply a bias voltage to a channel region.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: November 17, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Masayuki Masukawa, Masaru Seto, Keisuke Oosawa
  • Patent number: 7368349
    Abstract: A semiconductor memory device includes: a laminated body which has a floating-gate-forming groove and includes a semiconductor support layer, an impurity diffusion layer, an ion-implantation-damage protection film, and an interlayer insulating film; a floating-gate-insulating film; a floating gate disposed on the floating-gate-insulating film so as to be buried in the floating-gate-forming groove; a control-gate-insulating film disposed on a surface area of the floating gate; and a control gate disposed on the control-gate-insulating film above the floating gate, wherein the floating-gate-insulating film contacts with the semiconductor support layer at the bottom of the floating-gate-forming groove, the floating-gate-insulating film contacts with the impurity diffusion layer, the ion-implantation-damage protection film, and the interlayer insulating film at the side wall of the floating-gate-forming groove.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: May 6, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masaru Seto, Junya Maneki
  • Publication number: 20080099876
    Abstract: The present invention provides a method of manufacturing a semiconductor device, which comprises steps of forming a plurality of wirings on a first insulting film formed on a semiconductor substrate so as to adjoin one another, forming a second insulating film on the first insulating film by a plasma CVD method and covering the wirings with the second insulating film in such a manner that air gaps are formed between the respective adjacent wirings, forming a third insulating film on the second insulating film by a high density plasma CVD method, and forming a fourth insulating film high in moisture resistance on the third insulating film.
    Type: Application
    Filed: October 5, 2007
    Publication date: May 1, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Masaru Seto
  • Publication number: 20080057669
    Abstract: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a plasma state including oxygen and silicon on an inner surface of the trench while applying no bias voltage (or a relatively low voltage), and a second step of filling the material in a plasma state including oxygen and silicon in the trench while applying a bias voltage (or a relatively high voltage).
    Type: Application
    Filed: July 24, 2007
    Publication date: March 6, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Masaru Seto
  • Publication number: 20080048238
    Abstract: There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of fabricating the nonvolatile semiconductor memory. Plural word lines and plural bit lines are disposed on a semiconductor substrate, and there are memory cells at intersecting portions of the word lines and the bit lines. At contact portions of the word lines and metal wires of an upper layer, polysilicon regions, which include the contact portions, are formed beneath a polysilicon forming the word lines, as an etching stop layer at a time of forming contacts.
    Type: Application
    Filed: July 27, 2007
    Publication date: February 28, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO. LTD.
    Inventor: Masaru Seto
  • Patent number: 7336762
    Abstract: An X-ray CT apparatus includes a host and a scanner that executes a scan based on a scan program communicated from the host by means of communicating means. The X-ray CT apparatus also includes a communicating means which collectively communicate the calculated values of X-ray applied amounts at every scan positions or original data for the calculation of the amount of X-ray application even with respect to unprogrammed scan positions. Each of the calculated values of X-ray applied amounts corresponds to a tube current value of an X-ray tube. The original data for the calculation of the amount of X-ray application corresponds to X-ray penetrated image data of a subject.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: February 26, 2008
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Masaru Seto, Yasushi Sato
  • Patent number: 7336758
    Abstract: A method to check a tissue located in the vicinity of an object of examination when a treatment instrument such as a puncture needle is inserted into a subject, wherein a first planar image construction block included in an image construction unit reconstructs in real time two-dimensional planar images, which represent subject's slice planes, on the basis of projection data. A stereoscopic image construction block included in the image construction unit constructs three-dimensional stereoscopic images, which represent the subject's slice planes, on the basis of projection data. The planar images constructed by the first planar image construction block are displayed in real time on the screen of a display unit, and the stereoscopic images constructed by the stereoscopic image construction block are displayed on the screen of the display unit while being juxtaposed with the first planar images constructed by the first planar image construction block.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: February 26, 2008
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Masaru Seto, Yasushi Sato
  • Publication number: 20070272968
    Abstract: Separate first and second floating gates for attracting carriers transferring in a transistor structure having a channel region and first and second main electrode regions into charge storage films therebelow are formed so as to largely face a control gate. The control gate between the separate first and second floating gates faces to the channel region via thin interlayer insulating layer. Therefore, a semiconductor device according to the present invention can inject electrons the charge storage film without causing writing errors in a writing operation, and therefore can increase in reliability thereof, control a writing voltage, prevent loss of the electrons stored in the charge storage film, and reliably apply a bias voltage to a channel region.
    Type: Application
    Filed: April 20, 2007
    Publication date: November 29, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Masayuki Masukawa, Masaru Seto, Keisuke Oosawa