Patents by Inventor Masaru Shimbo

Masaru Shimbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5089134
    Abstract: A silica glass filter comprises a porous support body composed of amorphous silica particles as a porous sintered body and having a purity of 99.9% or more and containing 150 ppm or less in total of impurities including alkali, alkali metal, heavy metal and/or elements of III B group, and a filtration layer formed on the support body. The filtration layer is composed of amorphous silica particles as a porous sintered body in a fine mode and has substantially the same purity as that of the support body.
    Type: Grant
    Filed: December 26, 1990
    Date of Patent: February 18, 1992
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Kuniko Ando, Koichi Shiraishi, Masaru Shimbo, Shunzo Shimai
  • Patent number: 4837186
    Abstract: A silicon semiconductor substrate includes an insulating layer embedded therein. The silicon semiconductor substrate comprises a first silicon plate, an insulating layer embedded in the first silicon plate so that the surfaces of the silicon plate and the insulating layer are in a mirror surface, and a second silicon plate united with the first silicon plate and the insulating layer at the mirror surface of the first silicon plate and the insulating layer. The insulating layer is used for forming an isolated region in the second silicon plate.
    Type: Grant
    Filed: August 12, 1987
    Date of Patent: June 6, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yu Ohata, Tsuyoshi Kuramoto, Masaru Shimbo
  • Patent number: 4791465
    Abstract: In a semiconductor sensor, the surfaces of first and second semiconductor substractes of a first conductivity type are made into flat surfaces by polishing the surfaces and are contacted each other so that the both substrates are bonded together. Source and claim regions are formed by diffusing an impurity of second conductivity type. The source and claim regions are separated through a through hole formed in the second substrate and are extended along the surface of the second substrate. An insulative layer is formed on the opposite surface of the second substrate and an inner surface of the through hole.
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: December 13, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Masaki Katsura, Hideaki Hiraki, Shigeki Uno, Masaru Shimbo, Kazuyoshi Furukawa
  • Patent number: 4738935
    Abstract: A method of manufacturing a compound semiconductor device has the steps of mirror-polishing a surface of each of two compound semiconductor substrates, bringing the mirror-polished surfaces of the two compound semiconductor substrates in contact with each other in a clean atmosphere and in a state wherein substantially no foreign substances are present therebetween, and annealing the compound semiconductor substrates which are in contact with each other so as to provide a bonded structure having a junction with excellent electrical characteristics at the interface.
    Type: Grant
    Filed: December 16, 1985
    Date of Patent: April 19, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Shimbo, Hiromichi Ohashi, Kazuyoshi Furukawa, Kiyoshi Fukuda
  • Patent number: 4700466
    Abstract: A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other.
    Type: Grant
    Filed: February 3, 1986
    Date of Patent: October 20, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Hiromichi Ohashi, Tsuneo Ogura, Masaru Shimbo
  • Patent number: 4671846
    Abstract: A method of bonding two single-crystal silicon bodies comprises the steps of: (i) mirror-polishing the contact surfaces of the bodies to reduce the surface roughness to 500A or less; (ii) removing contaminant from the mirror-polished surfaces; and (iii) bringing the surfaces into mutual contact so that substantially no foreign substance enter the gap between these surfaces.
    Type: Grant
    Filed: August 16, 1984
    Date of Patent: June 9, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Shimbo, Kiyoshi Fukuda
  • Patent number: 4638552
    Abstract: A method of manufacturing a semiconductor substrate having a modified layer therein comprises the steps of mirror-polishing one surface of each of first and second semiconductor plates, forming a modified layer on at least one of the polished surfaces of the first and second semiconductor plates, and bonding the polished surfaces of the first and second semiconductor plates with each other in a clean atmosphere.
    Type: Grant
    Filed: February 14, 1985
    Date of Patent: January 27, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Shimbo, Kiyoshi Fukuda, Yoshiaki Ohwada
  • Patent number: 4542105
    Abstract: A glass composition for covering a semiconductor element. The glass composition has excellent resistance to chemicals and excellent electric characteristics. The glass composition includes 3 to 8% by weight of Al.sub.2 O.sub.3, 35 to 45% by weight of SiO.sub.2, 10 to 30% by weight of ZnO, 5 to 30% by weight of PbO, 1 to 10% by weight of B.sub.2 O.sub.3, and more than 5% but not exceeding 20% by weight of an alkaline earth metal oxide selected from the group consisting of MgO, CaO, SrO and BaO, where the maximum contents of MgO, CaO, SrO and BaO are 7% by weight, 3% by weight, 7% by weight, and 15% by weight, respectively.
    Type: Grant
    Filed: December 29, 1982
    Date of Patent: September 17, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kazuyoshi Furukawa, Masaru Shimbo, Kiyoshi Fukuda, Katsujirou Tanzawa
  • Patent number: 4341980
    Abstract: A flat display device comprises a vacuum envelope constituted by a back base plate consisting of an elastic metal plate and a display panel and accommodating a thermionic cathode structure and a plurality of electrode structures for controlling the electron beams emitted from the thermionic cathode structure. The thermionic cathode structure is divided into a plurality of sections each including a plurality of coiled thermionic cathode heaters connected in parallel and arranged such that each corresponds to each of picture element regions provided on the back side of the display panel. Voltage supply terminals for supplying power to the parallel coiled heaters in each section are led out through the back base plate via insulating members.
    Type: Grant
    Filed: September 4, 1980
    Date of Patent: July 27, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Mikio Noguchi, Kazuho Kobayashi, Shigeo Takenaka, Masaru Shimbo