Abstract: A demand prediction device derives a first exponential function indicating the time-series transition of the number of bookings until a service provision time point for a first customer group based on the transition of the number of bookings until a time point t1 for the first group. A demand prediction device derives a second exponential function indicating the time-series transition of the number of bookings until a service provision time point for a second customer group based on the transition of the number of bookings until a time point t2 for the second customer group different from the first group. The demand prediction device generates information supporting a service providing entity based on the time-series transition of the number of bookings until an analysis target time point for the first customer group indicated by the first exponential function and that for the second customer group by the second exponential function.

Abstract: A word line WLA of A port is activated based on a clock signal ACLK, and a word line WLB of B port is activated based on a port setting signal RDXA indicating that A port is a selected state. In addition thereto, a bit line of B port is precharged. A state in a simultaneous access operation is reproduced by activating the word line WLB during a time period of activating the word line WLA regardless of a delay difference of the clock signal and maintaining Vds of an access transistor of A port at a constant value.

Abstract: A word line WLA of A port is activated based on a clock signal ACLK, and a word line WLB of B port is activated based on a port setting signal RDXA indicating that A port is a selected state. In addition thereto, a bit line of B port is precharged. A state in a simultaneous access operation is reproduced by activating the word line WLB during a time period of activating the word line WLA regardless of a delay difference of the clock signal and maintaining Vds of an access transistor of A port at a constant value.

Abstract: The present invention enables to design a semiconductor integrated circuit with a small chip area and a small number of wiring layers at a low cost for a short time. In the present design method of the semiconductor integrated circuit, a first wiring group (a horizontal power wiring and horizontal ground wirings) and a second wiring group (a horizontal power wiring and horizontal ground wirings), which are opposite to each other, are arranged at the outside of a macro outer frame, a third wiring group (a vertical power wiring and a vertical ground wiring) is arranged to correspond to a power terminal and a ground terminal on a macro cell, and these first and second wiring groups are connected to the power terminal and the ground terminal by the third wiring group.

Abstract: The present invention enables to design a semiconductor integrated circuit with a small chip area and the number of wiring layers at a low cost for a short time. In the present design method of the semiconductor integrated circuit, a first wiring group (a horizontal power wiring and horizontal ground wirings) and a second wiring group (a horizontal power wiring and horizontal ground wirings), which are opposite to each other, are arranged at the outside of a macro outer frame, a third wiring group (a vertical power wiring and a vertical ground wring) is arranged to correspond to a power terminal and a ground terminal on a macro cell, and these first and second wiring groups are connected to the power terminal and the ground terminal by the third wiring group.