Patents by Inventor Masaru Sumi

Masaru Sumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963485
    Abstract: A natural invasion promoting method that is environmentally friendly, easy to carry out, can cope with a wide range of areas and inclined surfaces, achieves efficient natural invasion, and can satisfactorily promote greening on a soil surface of interest, and a spraying material used in the method are provided. A natural invasion promoting method including: spraying a spraying material containing live algae on a soil surface; breeding the live algae; and also directly or indirectly catching flying seeds or spores by a tacky substance secreted on surfaces of the live algae or a catching structure composed of the live algae to promote greening on the soil surface.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 23, 2024
    Assignees: NIPPON KOEI CO., LTD., NIKKEN SOHONSHA CORPORATION
    Inventors: Mineto Tomisaka, Masaru Onodera, Fumiko Iwaki, Hisako Sanada, Taketo Nakano, Nobuo Mori, Ryo Sumi, Kanya Tokunaga
  • Patent number: 6389686
    Abstract: A process for fabricating thin multi-layer circuit boards. A substrate is disposed over a heat-accumulating block adjacent thereto so that it is uniformly heated from the back side thereof during the pre-baking.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: May 21, 2002
    Assignee: Fujitsu Limited
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama
  • Publication number: 20010015008
    Abstract: A process for fabricating thin multi-layer circuit boards which allow the electrical conduction of remodeling pads to be easily cut do not use etching for gold, avoid the lift-off method for forming a thin chromium film on the wiring pattern layer, allow a defective wiring pattern layer to be removed, and which uses uniform heating of the substrate, from the back side thereof, at the time of pre-baking. A barrier metal (60) is excluded from a portion where the electrical conduction of a remodeling pad (62b) is to be cut (FIGS. 1 to 16). Alternatively, gold-plating resist is formed in order to avoid the etching for gold (FIGS. 17 to 19). Alternatively, a thin chromium film is formed in advance by etching on the wiring pattern layer (FIGS. 27 to 33). Alternatively, a metallic barrier film (122) is formed on each of the wiring pattern layers so that the wiring pattern layer can be removed without affecting other wiring pattern layers (FIGS. 36 to 42).
    Type: Application
    Filed: December 1, 2000
    Publication date: August 23, 2001
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama
  • Patent number: 6184476
    Abstract: A thin multi-layer circuit board having alternately stacked wiring pattern layers, including a top wiring pattern layer and insulating layers on an insulating plate-like substrate. The wiring pattern layers are electronically connected through vias in the insulating layers to form a predetermined circuit pattern by said wiring pattern layers. A metallic barrier layer is formed on the top wiring pattern layer, except at an exclusion zone of the metallic barrier layer. An electronic part-mounting pad layer and a remodeling pad layer are formed on the metallic barrier layer. The remodeling pad layer is arranged adjacent the electronic part-mounting pad layer, with the exclusion zone therebetween.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Ltd.
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama
  • Patent number: 5679268
    Abstract: A process for fabricating thin multi-layer circuit boards which allow the electrical conduction of remodeling pads to be easily cut do not use etching for gold, avoid the lift-off method for forming a thin chromium film on the wiring pattern layer, allow a defective wiring pattern layer to be removed, and which uses uniform heating of the substrate, from the back side thereof, at the time of pre-baking. A barrier metal (60) is excluded from a portion where the electrical conduction of a remodeling pad (62b) is to be cut (FIGS. 1 to 16). Alternatively, gold-plating resist is formed in order to avoid the etching for gold (FIGS. 17 to 19). Alternatively, a thin chromium film is formed in advance by etching on the wiring pattern layer (FIGS. 27 to 33). Alternatively, a metallic barrier film (122) is formed on each of the wiring pattern layers so that the wiring pattern layer can be removed without affecting other wiring pattern layers (FIGS. 36 to 42).
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: October 21, 1997
    Assignee: Fujitsu Limited
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama