Abstract: An error detection code generating device includes: a detector configured to detect a number of changed bits, which indicates a number of bits changed between transmitted data and a parity of a previous session and transmitted data and a parity of a current session; a generator configured to generate a first add code for a detection of an error based on the number of changed bits detected by the detector and the parity of the transmitted data of the current session; and a compression circuit configured to compress the first add signal generated by the generator and generate a second add code to be added to the transmitted data of the current session.

Abstract: A reception circuit that receives data by serial communication in a plurality of lanes and includes a plurality of error checking units each of which checks presence of an error in the received data, a plurality of memories each of which stores the received data, and a processing unit that reads the received data from the plurality of memories, and outputs a read data. The lanes include a redundant lane that transmits redundant data, the received data is stored in a first area of a plurality of areas included in each of the memories, and other received data received next to the received data is stored in a second area. When there is an error in any one of the pieces of received data stored in the respective first areas, the processing unit generates correct data using the redundant data stored in the first area, and outputs it.

Abstract: A circuit includes a memory including a first and a second memory region each configured to store coupling information, a first logic circuit including a plurality of first logic elements coupled with each other based on the coupling information stored in the first memory region, a second logic circuit including a plurality of second logic elements coupled with each other based on the coupling information stored in the second memory region, a writing circuit configured to write the coupling information in each of the first and the second memory region when a first output data of the first logic circuit does not identify to a second output data of the second logic circuit, and a determination circuit configured to determine whether or not the first output data identifies to the second output data after the coupling information is written in each of the first and the second memory region.

Abstract: A synchronization circuit that synchronizes received data, includes: a determiner for determining whether or not data with a phase of a internal clock can be stably captured by the synchronization circuit, when the synchronization circuit accepts the data received from another device connected to the synchronization circuit with the phase of the internal clock of the synchronization circuit; a first flip-flop circuit accepting the data and the internal clock, capturing the data with the phase of the internal clock and synchronizing the data, when the determiner determines that the synchronization circuit can stably capture the data; a second flip-flop accepting the data and an inverted internal clock that has a phase obtained by inverting the phase of the internal clock, capturing the data with the phase of the inverted internal clock, and synchronizing the data, when the determiner determines that the synchronization circuit can not stably capture the data.

Abstract: Each of the plurality of second processing units includes: a counter that counts a count value in synchronization with such a counter included in each remaining second processing unit; a register that holds the count value of the counter; and a control unit that stores the count value, which is counted by the counter when receiving a measurement instruction from the first processing unit, as a receipt-timing count value into the register and notifies the first processing unit of the held receipt-timing count value, and the first processing unit calculates one or more differences between a plurality of the receipt-timing count values notified from the second processing units as a transmitting delay difference from the first processing unit to each of the plurality of second processing units.

Abstract: A reception circuit that receives data by serial communication in a plurality of lanes and includes a plurality of error checking units each of which checks presence of an error in the received data, a plurality of memories each of which stores the received data, and a processing unit that reads the received data from the plurality of memories, and outputs a read data. The lanes include a redundant lane that transmits redundant data, the received data is stored in a first area of a plurality of areas included in each of the memories, and other received data received next to the received data is stored in a second area. When there is an error in any one of the pieces of received data stored in the respective first areas, the processing unit generates correct data using the redundant data stored in the first area, and outputs it.

Abstract: A data processing circuit includes a receive circuit that receives data including a control bit for controlling a process of the data, a hold circuit that holds the received data, an error detection circuit that detects an error in the received data, a first correction circuit that corrects the received data when an error of the control bit in the received data is detected, and outputs the corrected data, and an output select circuit that outputs data held in the hold circuit when no error is detected in the control bit, and outputs the corrected data outputted from the first correction circuit when an error is detected in the control bit.

Abstract: A synchronization circuit that synchronizes received data, includes: a determiner for determining whether or not data with a phase of a internal clock can be stably captured by the synchronization circuit, when the synchronization circuit accepts the data received from another device connected to the synchronization circuit with the phase of the internal clock of the synchronization circuit; a first flip-flop circuit accepting the data and the internal clock, capturing the data with the phase of the internal clock and synchronizing the data, when the determiner determines that the synchronization circuit can stably capture the data; a second flip-flop accepting the data and an inverted internal clock that has a phase obtained by inverting the phase of the internal clock, capturing the data with the phase of the inverted internal clock, and synchronizing the data, when the determiner determines that the synchronization circuit can not stably capture the data.

Abstract: A data processing circuit includes a receive circuit that receives data including a control bit for controlling a process of the data, a hold circuit that holds the received data, an error detection circuit that detects an error in the received data, a first correction circuit that corrects the received data when an error of the control bit in the received data is detected, and outputs the corrected data, and an output select circuit that outputs data held in the hold circuit when no error is detected in the control bit, and outputs the corrected data outputted from the first correction circuit when an error is detected in the control bit.

Abstract: A bidirectional bus control circuit to which first and second direction signals instructing bus directions are input and which inputs and outputs a clock signal and data signal includes a first bidirectional buffer that switches an input or output direction of the clock signal in accordance with the second direction signal, a second bidirectional buffer that switches an input or output direction of the data signal in accordance with the second direction signal, and a data confirmation unit that confirms a data signal input to the second bidirectional buffer and invalidates the confirmation of the data signal in accordance with switching of the signal direction instructed by the first direction signal from the input direction to the output direction, the switching of the signal direction instructed by the first direction signal occurring before the switching of the signal direction instructed by the second direction.

Abstract: A bidirectional bus control circuit to which first and second direction signals instructing bus directions are input and which inputs and outputs a clock signal and data signal includes a first bidirectional buffer that switches an input or output direction of the clock signal in accordance with the second direction signal, a second bidirectional buffer that switches an input or output direction of the data signal in accordance with the second direction signal, and a data confirmation unit that confirms a data signal input to the second bidirectional buffer and invalidates the confirmation of the data signal in accordance with switching of the signal direction instructed by the first direction signal from the input direction to the output direction, the switching of the signal direction instructed by the first direction signal occurring before the switching of the signal direction instructed by the second direction.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode tab. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.