Abstract: A multipurpose speed controllable processor composed of control memories for storing microprograms, register groups for storing instructions as well as data and the internal states of the processor, all of which serve as parts of the micro instructions, and arithmetic logic units which execute the micro instructions from the microprogram. The arithmetic logic units operate in accordance with operand addresses and codes designated in the micro instructions. Switches are provided for transferring the operand addresses of the micro instructions from the control memories to the register groups, for transferring the operands from the register groups to the arithmetic logic units, for transferring to the register groups the results of the operation of the arithmetic logic units, for transferring the operation codes from the control memories to the arithmetic units and for transferring to a control unit special status information of the operation results in the arithmetic logic units.