Abstract: A structure of a non-volatile flash memory, in which a punch-through current is suppressed and the area of a memory cell is reduced, is provided. The non-volatile flash memory being a NOR type non-volatile flash memory provides floating gates and a common source line, and drains. And at the structure of the non-volatile flash memory, a region overlapped one of the drains and one of the floating gates in a memory cell is larger than a region overlapped the common source and one of the floating gates in the memory cell.

Abstract: The present invention provides a method of forming a floating gate memory cell structure. The method comprising the following steps. A dummy pattern is selectively formed on a predetermined region of a semiconductor substrate. Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask. Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction. The dummy pattern is removed so that a channel region defined between the source and drain regions is shown. A first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films. A single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed.

Abstract: The present invention provides a method o forming a floating gate memory cell structure. The method comprising the following steps. A dummy pattern is selectively formed on a predetermined region of a semiconductor substrate. Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask. Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction. The dummy pattern is removed so that a channel region defined between the source and drain regions is shown. A first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films. A single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed.

Abstract: In a semiconductor memory device, such as a flash memory device, a conductor layer of metal or metal compound having high refractoriness, such as titanium nitride, is formed on a conductor or wiring formed by a buried diffusion layer to reduce resistance thereof. In the present invention, such conductor layer is formed by using small number of process steps and without using photolithography process. For example, after forming the buried diffusion layer for source and drain regions by ion implantation using each floating gate and dummy gate as a mask, titanium nitride is deposited throughout a substrate. Thereafter, by using oxide film growth and etching back process, an oxide film layer remaining on the titanium nitride layer between the floating gate and the dummy gate is fabricated. Then, the titanium nitride layer on the floating gate and on the dummy gate is removed by using this remained oxide film layer as a mask, without using any photolithography process.

Abstract: A structure of a non-volatile flash memory, in which a punch-through current is suppressed and the area of a memory cell is reduced, is provided. The non-volatile flash memory being a NOR type non-volatile flash memory provides floating gates and a common source line, and drains. And at the structure of the non-volatile flash memory, a region overlapped one of the drains and one of the floating gates in a memory cell is larger than a region overlapped the common source and one of the floating gates in the memory cell.

Abstract: The object of the present invention is to provide a non-volatile semiconductor memory device which is capable of increasing a integration density of a memory cell by increasing the number of states to be expressed with one memory cell. A non-volatile semiconductor memory device of the present invention has a structure in which two floating gates (3, 4) under one control gate (5) having a minimum dimension are provided, each of two floating gates is able to express two values in accordance with existences of stored charges whereby one memory cell is able to express four values and the widths of the two floating gates are different.

Abstract: For each memory cell of a non-volatile memory, first and second semiconductor regions are provided in a substrate to serve as a source and a drain respectively and a channel region is formed therebetween. On different areas of the channel region are provided first and second floating gates, on which a control gate is formed. Third and fourth semiconductor regions of the same conductivity type as that of the substrate are respectively located below the first and second floating gates and respectively adjacent the drain and source regions. The impurity concentration of the third and fourth semiconductor regions is higher than that of the substrate.

Abstract: The object of the present invention is to provide a non-volatile semiconductor memory device which is capable of increasing a integration density of a memory cell by increasing the number of states to be expressed with one memory cell.A non-volatile semiconductor memory device of the present invention has a structure in which two floating gates (3, 4) under one control gate (5) having a minimum dimension are provided, each of two floating gates is able to express two values in accordance with existences of stored charges whereby one memory cell is able to express four values.

Abstract: A floating gate type field effect transistor has a floating gate electrode formed of p-type polysilicon and a control gate electrode capacitively coupled to the floating gate electrode, and an erasing pulse signal is applied to the control gate electrode so that accumulated electrons are drifted in a depletion layer formed in the floating gate electrode toward a lower insulating layer, thereby evacuating the electrons to a silicon substrate without deterioration of the lower insulating layer.