Patents by Inventor Masaru Wakabayashi
Masaru Wakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11657654Abstract: This disclosure makes vehicle passage at a tollbooth on a vehicle road smoother. A plurality of candidate lanes are selected based on whether or not a first vehicle scheduled to pass through a tollbooth is an ETC vehicle, and the type of each lane at the tollbooth. Moreover, a predicted value in correlation with a required time predicted to be required for passing through the tollbooth is calculated for each candidate lane. Further, a recommended lane that is recommended for the first vehicle to travel is determined from the plurality of candidate lanes based on the predicted value for each candidate lane.Type: GrantFiled: March 29, 2021Date of Patent: May 23, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashige Hori, Masaru Wakabayashi, Yoko Sakurai, Ken Ishikawa
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Publication number: 20220180677Abstract: An alighting point guide system includes an acquisition portion configured to acquire an alighting point guide request from an occupant of a vehicle, and a guide portion configured to provide a guide to an alighting point. When the number of occupants of the vehicle as a transmission source of the alighting point guide request is larger than a reference number set in advance, the guide portion selects, as the alighting point, a point where at least either one value of a statistic value about a door-open time detected previously and a statistic value about the number of times of door opening that is detected previously is equal to or more than a threshold with preference to a point where the at least either one value is less than the threshold.Type: ApplicationFiled: November 24, 2021Publication date: June 9, 2022Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yoko SAKURAI, Masaru OHASHI, Ken ISHIKAWA, Takashige HORI, Masaru WAKABAYASHI, Shin MAEYAMADA
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Publication number: 20220163340Abstract: A server apparatus includes a communication interface, a memory configured to store information on an area in which a terminal apparatus mounted in a vehicle can connect to a predetermined communication network, and a controller configured to transmit and receive information to and from the terminal apparatus via the communication interface. Upon receiving, from the terminal apparatus, information on a departure point and a destination of the vehicle and designation information designating a connection to the predetermined communication network, the controller is configured to transmit, to the terminal apparatus, information necessary for the terminal apparatus to output information on a first route from the departure point through the area to the destination.Type: ApplicationFiled: November 16, 2021Publication date: May 26, 2022Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashige HORI, Masaru WAKABAYASHI
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Publication number: 20210304520Abstract: This disclosure makes vehicle passage at a tollbooth on a vehicle road smoother. A plurality of candidate lanes are selected based on whether or not a first vehicle scheduled to pass through a tollbooth is an ETC vehicle, and the type of each lane at the tollbooth. Moreover, a predicted value in correlation with a required time predicted to be required for passing through the tollbooth is calculated for each candidate lane. Further, a recommended lane that is recommended for the first vehicle to travel is determined from the plurality of candidate lanes based on the predicted value for each candidate lane.Type: ApplicationFiled: March 29, 2021Publication date: September 30, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashige HORI, Masaru WAKABAYASHI, Yoko SAKURAI, Ken ISHIKAWA
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Publication number: 20210264775Abstract: A server includes a control unit configured to: determine based on probe data acquired by a first vehicle whether the first vehicle is parked or stopped on a road; determine based on probe data acquired by one or more second vehicles located near the first vehicle whether the first vehicle is affecting traffic flow on the road, when the control unit determines that the first vehicle is parked or stopped; and output an alert when the control unit determines that the first vehicle is affecting the traffic flow on the road.Type: ApplicationFiled: January 7, 2021Publication date: August 26, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashige HORI, Masaru WAKABAYASHI, Yoko SAKURAI, Ken ISHIKAWA
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Patent number: 10527872Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.Type: GrantFiled: October 31, 2017Date of Patent: January 7, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki
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Patent number: 10317769Abstract: In a semiconductor device connected to a first optical waveguide, a phase modulation unit, and a second optical waveguide in this order and having an optical modulator guiding light in a first direction, the phase modulation unit includes: a semiconductor layer whose length in the first direction is larger than a width in a second direction orthogonal to the first direction and which is made of monocrystalline silicon; a core part serving as an optical waveguide region formed on the semiconductor layer, and extending in the first direction; a pair of slab parts arranged on both sides of the core part in the second direction; a first electrode coupled with one of the slab parts; and a second electrode coupled with the other of the slab parts. The core part has a p type semiconductor region and an n type semiconductor region extending in the first direction, and the second direction coincides with a crystal orientation <100> of the semiconductor layer.Type: GrantFiled: April 28, 2018Date of Patent: June 11, 2019Assignee: Renesas Electronics CorporationInventors: Shinichi Watanuki, Yasutaka Nakashiba, Masaru Wakabayashi
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Patent number: 10295743Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.Type: GrantFiled: August 17, 2015Date of Patent: May 21, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
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Patent number: 10162110Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.Type: GrantFiled: August 22, 2016Date of Patent: December 25, 2018Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Tatsuya Usami, Keiji Sakamoto, Yoshiaki Yamamoto, Shinichi Watanuki, Masaru Wakabayashi, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
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Publication number: 20180341165Abstract: In a semiconductor device connected to a first optical waveguide, a phase modulation unit, and a second optical waveguide in this order and having an optical modulator guiding light in a first direction, the phase modulation unit includes: a semiconductor layer whose length in the first direction is larger than a width in a second direction orthogonal to the first direction and which is made of monocrystalline silicon; a core part serving as an optical waveguide region formed on the semiconductor layer, and extending in the first direction; a pair of slab parts arranged on both sides of the core part in the second direction; a first electrode coupled with one of the slab parts; and a second electrode coupled with the other of the slab parts. The core part has a p type semiconductor region and an n type semiconductor region extending in the first direction, and the second direction coincides with a crystal orientation <100> of the semiconductor layer.Type: ApplicationFiled: April 28, 2018Publication date: November 29, 2018Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA, Masaru WAKABAYASHI
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Publication number: 20180052338Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.Type: ApplicationFiled: October 31, 2017Publication date: February 22, 2018Inventors: Hiroyuki KUNISHIMA, Yasutaka NAKASHIBA, Masaru WAKABAYASHI, Shinichi WATANUKI
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Patent number: 9835882Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.Type: GrantFiled: May 11, 2016Date of Patent: December 5, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki
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Publication number: 20170068047Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.Type: ApplicationFiled: August 22, 2016Publication date: March 9, 2017Inventors: TATSUYA USAMI, KEIJI SAKAMOTO, YOSHIAKI YAMAMOTO, SHINICHI WATANUKI, MASARU WAKABAYASHI, TOHRU MOGAMI, TSUYOSHI HORIKAWA, KEIZO KINOSHITA
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Patent number: 9508662Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.Type: GrantFiled: August 17, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
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Publication number: 20160334573Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Inventors: Hiroyuki KUNISHIMA, Yasutaka NAKASHIBA, Masaru WAKABAYASHI, Shinichi WATANUKI
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Publication number: 20160054521Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.Type: ApplicationFiled: August 17, 2015Publication date: February 25, 2016Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
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Publication number: 20160056115Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.Type: ApplicationFiled: August 17, 2015Publication date: February 25, 2016Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
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Patent number: 6638816Abstract: A first conductive layer of metal silicide, a silicon layer, an insulating layer, and a second conductive layer of metal or metal silicide are deposited in the order named on a surface of a a semiconductor substrate. Thereafter, the second conductive layer and the insulating layer are patterned to expose the silicon layer. The exposed silicon layer and the first conductive layer are patterned, thereby forming an MIM capacitance circuit.Type: GrantFiled: April 9, 2002Date of Patent: October 28, 2003Assignee: NEC Electronics CorporationInventor: Masaru Wakabayashi
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Patent number: 6472287Abstract: The present invention aims to suppress certainly the single-crystallizing in polycrystalline silicon that is to compose an emitter electrode, as well as to prevent the interface oxide film from remaining, when a heat treatment is conducted to diffuse dopants, and thereby it is also aimed to regulate the emitter dopant concentrations according to the design as well as to lower the emitter electrode resistance, which will provide a stable hFE; and further, the present invention aims to prevent anomalous bodies such as water-marks to be accidentally produced in a cleaning step following dry etching step to form an emitter electrode, and thereby to achieve an increase in yield as well as an enhancement of device reliability; in the process of the present invention, after an insulating film 4 and a first polycrystalline silicon film 5 are selectively dry etched to form a contact hole, a substrate is cleaned with such a cleansing agent as that composed of ammonia, hydrogen peroxide and water.Type: GrantFiled: March 6, 2002Date of Patent: October 29, 2002Assignee: NEC CorporationInventor: Masaru Wakabayashi
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Publication number: 20020127832Abstract: The present invention aims to suppress certainly the single-crystallization in polycrystalline silicon that is to compose an emitter electrode, as well as to prevent the interface oxide film from remaining, when a heat treatment is conducted to diffuse dopants, and thereby it is also aimed to regulate the emitter dopant concentrations according to the design as well as to lower the emitter electrode resistance, which will provide a stable hFE; and further, the present invention aims to prevent anomalous bodies such as water-marks to be accidentally produced in a cleaning step following dry etching step to form an emitter electrode, and thereby to achieve an increase in yield as well as an enhancement of device reliability; in the process of the present invention, after an insulating film 4 and a first polycrystalline silicon film 5 are selectively dry etched to form a contact hole, a substrate is cleaned with such a cleansing agent as that composed of ammonia, hydrogen peroxide and water.Type: ApplicationFiled: March 6, 2002Publication date: September 12, 2002Applicant: NEC CORPORATIONInventor: Masaru Wakabayashi