Patents by Inventor Masaru Yamada
Masaru Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12202552Abstract: A vehicle exterior member having a self-neutralizing function which can improve running characteristics and steering stability of a vehicle without impairing the design property has a fiber molded member containing a needle-punched nonwoven fabric or knitted fabric. The fibers constituting the fiber molded member contain a conductive fiber.Type: GrantFiled: March 10, 2020Date of Patent: January 21, 2025Assignees: HAYASHI TELEMPU CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kensaku Sakai, Hiroshi Suzuki, Koushi Yamada, Motoi Iida, Masaru Shirota
-
Publication number: 20240312805Abstract: According to the present disclosure, A method for manufacturing a semiconductor apparatus bonds a ring-shaped frame to an outer peripheral portion of a wafer, and comprises the steps of installing one of the wafer and the frame on a stage, holding another of the wafer and the frame in a chuck part in a pressure-bonding mechanism, activating a surface layer of the outer peripheral portion of the wafer and a surface layer of the frame by atom irradiation, and sandwiching the wafer and the frame between the stage and the chuck part and pressure-bonding the activated surface layers of the wafer and the frame using the pressure-bonding mechanism. An amorphous layer is formed on a bonding interface between the wafer and the frame pressure-bonded to each other.Type: ApplicationFiled: January 5, 2024Publication date: September 19, 2024Applicant: Mitsubishi Electric CorporationInventors: Kyohei AKIYOSHI, Yosuke NAKANISHI, Masaru YAMADA
-
Publication number: 20240175182Abstract: A sewing machine external unit includes: a holder holding fabric; a driver being detachable from a bed of a sewing machine and driving the holder along an upper surface of the bed; a pressing member moving in an up-down direction according to movement of a sewing needle in the up-down direction, pressing the fabric while the sewing needle is stuck in the fabric, and rising together with the sewing needle in response to the sewing needle coming out of the fabric and rising; a position detector detecting a position of the pressing member in the up-down direction; a signal output part outputting a signal to the sewing machine; and a controller outputting a needle drive signal for driving the sewing needle from the signal output part to the sewing machine, and controlling driving of the holder and/or the sewing needle based on a detection result of the position detector.Type: ApplicationFiled: November 28, 2023Publication date: May 30, 2024Applicant: JUKI CORPORATIONInventors: Takeshi ASAMI, Yoshiaki Abe, Masaru YAMADA, Eiichi Karasawa, Toshiaki Sakaeda, Takashi Shibuya, Honoka Iimura, Naofumi Fukuba
-
Publication number: 20240175180Abstract: The disclosure improves the quality of seams in sewing using a sewing machine, and includes: a holder holding fabric; a driver being detachable from a bed of a sewing machine and driving the holder along an upper surface of the bed; a position detector detecting a position of a sewing needle of the sewing machine in an up-down direction; and a controller controlling driving of the holder, which is performed by the driver, based on a detection result of the position detector.Type: ApplicationFiled: November 28, 2023Publication date: May 30, 2024Applicant: JUKI CORPORATIONInventors: Takeshi ASAMI, Yoshiaki Abe, Masaru YAMADA, Eiichi Karasawa, Toshiaki Sakaeda, Takashi Shibuya, Honoka Iimura, Naofumi Fukuba
-
Patent number: 10192851Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.Type: GrantFiled: July 11, 2018Date of Patent: January 29, 2019Assignee: Renesas Electronics CorporationInventors: Yoshinori Miyaki, Masaru Yamada
-
Publication number: 20180323168Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.Type: ApplicationFiled: July 11, 2018Publication date: November 8, 2018Inventors: Yoshinori MIYAKI, Masaru YAMADA
-
Patent number: 10032745Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.Type: GrantFiled: July 26, 2014Date of Patent: July 24, 2018Assignee: Renesas Electronics CorporationInventors: Yoshinori Miyaki, Masaru Yamada
-
Publication number: 20150031191Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.Type: ApplicationFiled: July 26, 2014Publication date: January 29, 2015Inventors: Yoshinori Miyaki, Masaru Yamada
-
Patent number: 8293157Abstract: A method of manufacturing a cellulose/gelatin composite viscose rayon filament that is characterized by including a process in which a spinning process is carried out while a viscose spinning solution is mixed with a gelatin crosslinking solution, which makes it possible to produce a cellulose/gelatin composite viscose rayon having uniform strength and elongation without yarn disconnection.Type: GrantFiled: May 10, 2006Date of Patent: October 23, 2012Assignee: Kurashiki Boseki Kabushiki KaishaInventors: Masaru Yamada, Kunihiro Ohshima
-
Patent number: 8084826Abstract: An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.Type: GrantFiled: February 3, 2009Date of Patent: December 27, 2011Assignee: Panasonic CorporationInventors: Kenshi Kanegae, Masaru Yamada
-
Patent number: 8034721Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.Type: GrantFiled: March 4, 2010Date of Patent: October 11, 2011Assignee: Panasonic CorporationInventors: Masaru Yamada, Akihiko Tsudumitani
-
Publication number: 20110001193Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: ApplicationFiled: September 15, 2010Publication date: January 6, 2011Applicant: PANASONIC CORPORATIONInventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
-
Patent number: 7821138Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: GrantFiled: March 17, 2009Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
-
Publication number: 20100159702Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.Type: ApplicationFiled: March 4, 2010Publication date: June 24, 2010Applicant: PANASONIC CORPORATIONInventors: Masaru YAMADA, Akihiko Tsudumitani
-
Patent number: 7696099Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the sidewall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.Type: GrantFiled: November 16, 2006Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Masaru Yamada, Akihiko Tsudumitani
-
Publication number: 20090200582Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: ApplicationFiled: March 17, 2009Publication date: August 13, 2009Applicant: PANASONIC CORPORATIONInventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
-
Publication number: 20090200615Abstract: An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.Type: ApplicationFiled: February 3, 2009Publication date: August 13, 2009Inventors: Kenshi KANEGAE, Masaru YAMADA
-
Publication number: 20090166919Abstract: A method of manufacturing a cellulose/gelatin composite viscose rayon filament that is characterized by including a process in which a spinning process is carried out while a viscose spinning solution is mixed with a gelatin crosslinking solution, which makes it possible to produce a cellulose/gelatin composite viscose rayon having uniform strength and elongation without yarn disconnection.Type: ApplicationFiled: May 10, 2006Publication date: July 2, 2009Inventors: Masaru Yamada, Kunihiro Ohshima
-
Patent number: 7446015Abstract: A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions.Type: GrantFiled: December 8, 2004Date of Patent: November 4, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasutoshi Okuno, Masaru Yamada
-
Publication number: 20070277509Abstract: Decreases in the volume of intake air to an engine in response to environmental changes results in an increase in amount of PM emissions. In view of this situation, a correction coefficient of fuel supply interval is calculated based on the variation in amount of PM emissions to adjust a reference fuel supply interval in order to determine an target fuel supply interval. By adjusting the fuel supply interval, a fuel supply amount appropriate to the variation in amount of PM emissions, thereby preventing clogging of the injection hole of a supplemental fuel valve, while maintaining fuel economy.Type: ApplicationFiled: May 29, 2007Publication date: December 6, 2007Inventors: Jun Tahara, Masaru Yamada, Tadashi Toyota