Patents by Inventor Masashi Agata
Masashi Agata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160132356Abstract: A management apparatus includes (A) an acceptance unit to accept an instruction to dynamically change a processor configuration in a system that includes plural processors, and (B) a processing unit to identify a performance value of a system corresponding to a processor configuration caused by instructed dynamic change, determine whether or not the identified performance value is equal to or greater than a requested performance value for the system, and perform a processing to change the processor configuration instructed by the accepted instruction, upon determining that the identified performance value is equal to or greater than the requested performance value.Type: ApplicationFiled: January 5, 2016Publication date: May 12, 2016Applicant: FUJITSU LIMITEDInventors: Makoto Kozawa, Masashi Agata
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Patent number: 9298663Abstract: An information processing apparatus includes an interface configured to be connected with a connection apparatus, an acquisition unit configured to acquire apparatus information including a configuration or an operation specification of the connection apparatus connected with the interface, a determination unit configured to determine a control program to control the connection apparatus according to the apparatus information, and a control unit configured to use the determined control program to control the connection apparatus, wherein the connection apparatus includes an expansion connection unit and an expansion apparatus connected with the expansion connection unit, and the acquisition unit includes a first acquisition unit configured to acquire first information including a configuration or an operation specification of the expansion connection unit connected with the interface, and a second acquisition unit configured to acquire second information including a configuration or an operation specificationType: GrantFiled: December 10, 2013Date of Patent: March 29, 2016Assignee: FUJITSU LIMITEDInventors: Juntaro Minezaki, Masashi Agata, Shinji Hiyama
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Publication number: 20150228358Abstract: An information processing device includes a storage unit and a processor. The storage unit stores margin information, which stores a specified margin indicating a length of time in which signal processing is operated normally, in association with the type of a memory and the operation environment. The processor causes the memory to perform signal processing. The processor also changes an operation timing and specifies a range of operation timings with which the signal processing may be performed normally. Furthermore, the processor acquires the specified range of the operation timing as a measured margin, and extracts a specified margin associated with a combination of the type of memory and the operation environment of a current information processing device from the margin information. Then, the processor judges that the memory is not operating normally in the information processing device when the acquired measured margin is shorter than the extracted specified margin.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Applicant: FUJITSU LIMITEDInventors: Masashi AGATA, Daisuke HARADA
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Publication number: 20140108693Abstract: An information processing apparatus includes an interface configured to be connected with a connection apparatus, an acquisition unit configured to acquire apparatus information including a configuration or an operation specification of the connection apparatus connected with the interface, a determination unit configured to determine a control program to control the connection apparatus according to the apparatus information, and a control unit configured to use the determined control program to control the connection apparatus, wherein the connection apparatus includes an expansion connection unit and an expansion apparatus connected with the expansion connection unit, and the acquisition unit includes a first acquisition unit configured to acquire first information including a configuration or an operation specification of the expansion connection unit connected with the interface, and a second acquisition unit configured to acquire second information including a configuration or an operation specificationType: ApplicationFiled: December 10, 2013Publication date: April 17, 2014Applicant: FUJITSU LIMITEDInventors: Juntaro Minezaki, Masashi AGATA, Shinji Hiyama
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Patent number: 8667315Abstract: A synchronization control apparatus includes a counter that carries out a counting and outputs resulting count information, a timeout time holder that holds a predetermined timeout time and outputs the timeout time, a comparator that compares the count information output from the counter and the timeout time output from the timeout time holder, a synchronization controller that monitors a synchronization between a first processor and a second processor by comparing an output from the first processor and an output from the second processor and starts a counting, when a mis-match of the outputs from the first processor and the second processor is detected and wherein the comparator detects that the count information and the timeout time match, the comparator stops either the first processor or second processor in which a synchronization delay has occurred.Type: GrantFiled: September 29, 2009Date of Patent: March 4, 2014Assignee: Fujitsu LimitedInventor: Masashi Agata
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Publication number: 20100088535Abstract: A synchronization control apparatus includes a counter that carries out a counting and outputs resulting count information, a timeout time holder that holds a predetermined timeout time and outputs the timeout time, a comparator that compares the count information output from the counter and the timeout time output from the timeout time holder, a synchronization controller that monitors a synchronization between a first processor and a second processor by comparing an output from the first processor and an output from the second processor and starts a counting, when a mis-match of the outputs from the first processor and the second processor is detected and wherein the comparator detects that the count information and the timeout time match, the comparator stops either the first processor or second processor in which a synchronization delay has occurred.Type: ApplicationFiled: September 29, 2009Publication date: April 8, 2010Applicant: Fujitsu LimitedInventor: Masashi AGATA
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Patent number: 7315479Abstract: A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.Type: GrantFiled: May 24, 2006Date of Patent: January 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomohiro Kurozumi, Masashi Agata, Osamu Ichikawa
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Patent number: 7203117Abstract: A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.Type: GrantFiled: October 7, 2005Date of Patent: April 10, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masashi Agata, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara
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Patent number: 7200025Abstract: Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.Type: GrantFiled: November 15, 2005Date of Patent: April 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Shirahama, Masashi Agata, Toshiaki Kawasaki, Ryuji Nishihara
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Patent number: 7193908Abstract: Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.Type: GrantFiled: August 12, 2005Date of Patent: March 20, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiaki Kawasaki, Masashi Agata, Masanori Shirahama, Ryuji Nishihara
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Patent number: 7184304Abstract: A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.Type: GrantFiled: July 29, 2005Date of Patent: February 27, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuji Nishihara, Masashi Agata, Toshiaki Kawasaki, Masanori Shirahama
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Publication number: 20060268633Abstract: A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.Type: ApplicationFiled: May 24, 2006Publication date: November 30, 2006Inventors: Tomohiro Kurozumi, Masashi Agata, Osamu Ichikawa
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Patent number: 7057956Abstract: A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.Type: GrantFiled: August 30, 2004Date of Patent: June 6, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Shirahama, Masashi Agata, Toshiaki Kawasaki, Ryuji Nishihara
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Publication number: 20060114708Abstract: Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.Type: ApplicationFiled: November 15, 2005Publication date: June 1, 2006Inventors: Masanori Shirahama, Masashi Agata, Toshiaki Kawasaki, Ryuji NIshihara
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Patent number: 7050347Abstract: In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.Type: GrantFiled: January 21, 2005Date of Patent: May 23, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuji Nishihara, Masashi Agata, Toshiaki Kawasaki, Masanori Shirahama
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Publication number: 20060083046Abstract: A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.Type: ApplicationFiled: October 7, 2005Publication date: April 20, 2006Inventors: Masashi Agata, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara
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Patent number: 7031199Abstract: A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.Type: GrantFiled: April 2, 2004Date of Patent: April 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Naoki Kuroda, Masashi Agata
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Publication number: 20060039209Abstract: Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.Type: ApplicationFiled: August 12, 2005Publication date: February 23, 2006Inventors: Toshiaki Kawasaki, Masashi Agata, Masanori Shirahama, Ryuji Nishihara
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Patent number: 7002865Abstract: A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.Type: GrantFiled: September 8, 2004Date of Patent: February 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masashi Agata, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara
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Publication number: 20060023538Abstract: A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.Type: ApplicationFiled: July 29, 2005Publication date: February 2, 2006Inventors: Ryuji Nishihara, Masashi Agata, Toshiaki Kawasaki, Masanori Shirahama