Abstract: An air conditioner system for a vehicle having an occupant compartment which includes a driver's occupying area and a front passenger's occupying area. The system includes a vent duct adapted to conduct a conditioned air. The vent duct defines a first passages opening to the driver's occupying area and a second passage opening to the front passenger's occupying area. First and second vent valves are disposed within the first and second passages, respectively. First and second actuators are drivingly connected to the first and second vent valves. A first sensor is so constructed and arranged as to detect insolation magnitude within the driver's occupying area and generate a first sensor signal indicative of the detected insolation magnitude within the driver's occupying area.

Abstract: The semiconductor integrated circuit having a built-in test circuit of the present invention is an IC having a circuit for screening products for shipment by measuring the maximum operating frequency of the IC by outputting the propagation state of a signal within the test circuit within an operation cycle of the IC, the circuit being composed of: an external clock pulse input terminal; a clock driver that inputs the external clock pulse and converts it to clock pulses of two phases, one being in phase with the external clock pulse and the other being in reverse phase; a test terminal into which is inputted a test execution signal; a one-shot circuit that generates a high-active output pulse when an active signal is inputted; a sequential circuit that performs transition of an output value in accordance with an output pulse from the one-shot circuit; a test circuit made up of a number n of latch circuits of identical or differing structure that hold and successively output to a next circuit a high-level signa

Abstract: A variable gain amplifier includes a first stage amplifying portion and a subsequent stage amplifying portion for amplifying an output from the first stage amplifying portion and outputting an amplified signal to an output terminal. The first stage amplifying portion includes first and second transistors having emitters connected to each other through a resistor based upon which an input dynamic range is determined, and first and second diodes which are connected to collectors of the transistors as loads thereof. A reference current is generated by a reference current generating portion. A control current generating portion generates a control current which is N times the reference current and supplied to the collectors of the first and second transistors. Currents flowing through the first and second diodes is sunk by a current sinking portion.

Abstract: A PLL circuit comprises a variable frequency divider (7) for frequency-dividing a signal having a reference frequency f.sub.1 with a frequency dividing ratio n.sub.1 or n.sub.2, a fixed frequency divider (8) for further frequency-dividing an output of the variable frequency divider with a frequency dividing ratio n.sub.0, to generate a first output signal and a second output signal which is out of phase by 90.degree. from the first output signal, multiplier (10) for multiplying an input signal by the second output signal, a comparator (11) for comparing an output of the multiplier with a predetermined reference voltage, and a D-type flip-flop (12) receiving as a D input an output of the comparator and receiving as a clock input the first output signal, an output of the D-type flip-flop (12) being applied to the variable frequency divider (7). When the second output signal leads the input signal by 90.degree.

Abstract: An improved FMX sterophonic broadcast receiver provided with countermeasures against transient noises, which includes a level detection circuit for detecting level of a detected stereo difference signal, and a level control circuit for controlling level of an expanded stereo difference signal according to an output signal of the level detection circuit. By the above arrangement of the present invention, since it is so arranged to cause the level control circuit to function when the degree of modulation becomes large so as to control the level of the stereo difference signal to be low, a level difference is produced between the stereo sum signal and the stereo difference signal for deterioration of the stereo separation degree upon matrixing at a matrix circuit for reduction of noises accordingly.

Abstract: An FMX stereophonic receiver receives an FMX stereophonic broadcast signal which includes a stereo sum signal, an uncompressed stereo difference signal, and a compressed stereo difference signal which is formed by modulating the uncompressed stereo difference signal by a quadrature modulation and being compressed.

Abstract: An FM/FMX stereophonic receiver is capable of receiving an FM or an FMX stereophonic broadcast signal. The FM stereophonic broadcast signal includes a stereo sum signal and stereo difference signal, whereas the FMX stereophonic broadcast signal further includes a compressed stereo difference signal and an FMX ID signal indicating the FMX stereophonic broadcast signal. The FM/FMX stereophonic receiver has a stereo demodulator for receiving said broadcast signal and for producing left and right stereo signals, a detector for detecting the field strength of the receiving signal, and a noise reducer, which may be a circuit for changing the mode from stereophonic mode to monaural mode or a high cut circuit for attenuating the signals of high frequency region, for reducing noise signals contained in the left and right stereo signals.

Abstract: In an AM stereo receiving apparatus for decoding an AM stereo broadcasting signal of an ISB system, an envelope detecting circuit 6 detects an output of an intermediate frequency amplifying circuit 5 and a DC removing circuit 7 removes a DC component therefrom, so that a stereo sum signal (L+R) is obtained. A quadrature detecting circuit 9 detects quadrature of the output of the intermediate frequency amplifying circuit 5. A multiplying circuit 10 multiplies the stereo sum signal (L+R), which is amplified a times as much by a first amplifying circuit 8, and the output of the quadrature detecting circuit 9. An addition circuit 12 adds the output of the quadrature detecting circuit 9, which is amplified b times as much by a second amplifying circuit 11, and the output of the multiplying circuit 10.

Abstract: An AM stereo receiver applicable to receive AM signals containing ID signals which represent different AM stereo systems. The AM stereo receiver includes an IF circuit for generating an IF signal based on a received signal, a PLL circuit for locking the frequency of the IF signal, a clock circuit for generating a clock signal based on a signal obtained from the PLL circuit, and ID signal detector for detecting any one of the ID signals and for producing a detected ID signal. A circuit for distinguishing which one of the different AM stereo systems does the detected ID signal represent includes a pulse generator for generating a first pulse signal having a pulse width as a function of the frequency of the detected ID signal, a counter for counting the number of the clock pulses occurring during said first pulse signal, and distinguish circuit for distinguishing each detected ID signal from different ID signals based on the counted result of the counter.