Patents by Inventor Masashi Arakawa
Masashi Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10923419Abstract: A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.Type: GrantFiled: August 21, 2019Date of Patent: February 16, 2021Assignee: Renesas Electronics CorporationInventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
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Publication number: 20190378796Abstract: A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
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Patent number: 10396549Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.Type: GrantFiled: March 12, 2018Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masashi Arakawa, Tadashi Fukui, Koji Takayanagi
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Publication number: 20180205225Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.Type: ApplicationFiled: March 12, 2018Publication date: July 19, 2018Applicant: Renesas Electronics CorporationInventors: Masashi ARAKAWA, Tadashi FUKUI, Koji TAKAYANAGI
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Publication number: 20180138121Abstract: A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Inventors: Takeshi IWAMOTO, Kazushi KONO, Masashi ARAKAWA, Toshiaki YONEZU, Shigeki OBAYASHI
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Patent number: 9948090Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.Type: GrantFiled: September 25, 2015Date of Patent: April 17, 2018Assignee: Renesas Electronics CorporationInventors: Masashi Arakawa, Tadashi Fukui, Koji Takayanagi
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Patent number: 9893013Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.Type: GrantFiled: October 20, 2016Date of Patent: February 13, 2018Assignee: Renesas Electronics CorporationInventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
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Publication number: 20170040261Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Takeshi IWAMOTO, Kazushi KONO, Masashi ARAKAWA, Toshiaki YONEZU, Shigeki OBAYASHI
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Patent number: 9508641Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.Type: GrantFiled: January 6, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
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Patent number: 9478493Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.Type: GrantFiled: January 6, 2015Date of Patent: October 25, 2016Assignee: Renesas Electronics CorporationInventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
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Publication number: 20160094027Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.Type: ApplicationFiled: September 25, 2015Publication date: March 31, 2016Applicant: Renesas Electronics CorporationInventors: Masashi ARAKAWA, Tadashi FUKUI, Koji TAKAYANAGI
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Publication number: 20160071572Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.Type: ApplicationFiled: November 16, 2015Publication date: March 10, 2016Inventors: Natsuki IKEHATA, Kazuo TANAKA, Takeo TOBA, Masashi ARAKAWA
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Patent number: 9214217Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.Type: GrantFiled: August 3, 2014Date of Patent: December 15, 2015Assignee: Renesas Electronics CorporationInventors: Natsuki Ikehata, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
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Publication number: 20150303144Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.Type: ApplicationFiled: January 6, 2015Publication date: October 22, 2015Inventors: Takeshi IWAMOTO, Kazushi KONO, Masashi ARAKAWA, Toshiaki YONEZU, Shigeki OBAYASHI
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Publication number: 20140334240Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.Type: ApplicationFiled: August 3, 2014Publication date: November 13, 2014Inventors: Natsuki Ikehata, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
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Patent number: 8803610Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.Type: GrantFiled: August 20, 2012Date of Patent: August 12, 2014Assignee: Renesas Electronics CorporationInventors: Natsuki Ikehata, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
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Patent number: 8723291Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.Type: GrantFiled: August 23, 2012Date of Patent: May 13, 2014Assignee: Renesas Electronics CorporationInventors: Toshiaki Yonezu, Takeshi Iwamoto, Shigeki Obayashi, Masashi Arakawa, Kazushi Kono
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Publication number: 20140021559Abstract: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.Type: ApplicationFiled: September 20, 2013Publication date: January 23, 2014Applicant: Renesas Electronics CorporationInventors: Takeshi IWAMOTO, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
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Publication number: 20130049864Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.Type: ApplicationFiled: August 20, 2012Publication date: February 28, 2013Inventors: Natsuki IKEHATA, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
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Publication number: 20130049166Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.Type: ApplicationFiled: August 23, 2012Publication date: February 28, 2013Inventors: Toshiaki YONEZU, Takeshi Iwamoto, Shigeki Obayashi, Masashi Arakawa, Kazushi Kono