Patents by Inventor Masashi Arakawa

Masashi Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923419
    Abstract: A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: February 16, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Publication number: 20190378796
    Abstract: A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Patent number: 10396549
    Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masashi Arakawa, Tadashi Fukui, Koji Takayanagi
  • Publication number: 20180205225
    Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Masashi ARAKAWA, Tadashi FUKUI, Koji TAKAYANAGI
  • Publication number: 20180138121
    Abstract: A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Takeshi IWAMOTO, Kazushi KONO, Masashi ARAKAWA, Toshiaki YONEZU, Shigeki OBAYASHI
  • Patent number: 9948090
    Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masashi Arakawa, Tadashi Fukui, Koji Takayanagi
  • Patent number: 9893013
    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: February 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Publication number: 20170040261
    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Application
    Filed: October 20, 2016
    Publication date: February 9, 2017
    Inventors: Takeshi IWAMOTO, Kazushi KONO, Masashi ARAKAWA, Toshiaki YONEZU, Shigeki OBAYASHI
  • Patent number: 9508641
    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Patent number: 9478493
    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: October 25, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Publication number: 20160094027
    Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 31, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Masashi ARAKAWA, Tadashi FUKUI, Koji TAKAYANAGI
  • Publication number: 20160071572
    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Natsuki IKEHATA, Kazuo TANAKA, Takeo TOBA, Masashi ARAKAWA
  • Patent number: 9214217
    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
    Type: Grant
    Filed: August 3, 2014
    Date of Patent: December 15, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Natsuki Ikehata, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
  • Publication number: 20150303144
    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Application
    Filed: January 6, 2015
    Publication date: October 22, 2015
    Inventors: Takeshi IWAMOTO, Kazushi KONO, Masashi ARAKAWA, Toshiaki YONEZU, Shigeki OBAYASHI
  • Publication number: 20140334240
    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
    Type: Application
    Filed: August 3, 2014
    Publication date: November 13, 2014
    Inventors: Natsuki Ikehata, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
  • Patent number: 8803610
    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Natsuki Ikehata, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
  • Patent number: 8723291
    Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 13, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Yonezu, Takeshi Iwamoto, Shigeki Obayashi, Masashi Arakawa, Kazushi Kono
  • Publication number: 20140021559
    Abstract: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Application
    Filed: September 20, 2013
    Publication date: January 23, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi IWAMOTO, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Publication number: 20130049864
    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 28, 2013
    Inventors: Natsuki IKEHATA, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
  • Publication number: 20130049166
    Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 28, 2013
    Inventors: Toshiaki YONEZU, Takeshi Iwamoto, Shigeki Obayashi, Masashi Arakawa, Kazushi Kono