Abstract: A circuit delay analyzing apparatus that analyzes a delay in a circuit including a plurality of transistors, and a first resistor coupled in a path commonly extended between a power source and the plurality of transistors, the circuit delay analyzing apparatus includes, a memory includes net list of the circuit, and a processor coupled to the memory, configured to read the net list and select first transistors from the plurality of transistors that are coupled to the path, produce a partial circuit that includes the first resister and the first transistors, delete the first register; add first copy resisters reproduced from the first resistor to the partial circuit; and analyze the delay in the partial circuit.

Abstract: When a sequential circuit to which a clock signal distributed by a first buffer included in a clock distribution circuit is input is added, in a case where a plurality of other sequential circuits are connected to the first buffer, a processor determines whether or not a distance between the sequential circuit to be added and the first buffer is between a maximum value and a minimum value of distances between the first buffer and the plurality of other sequential circuits based on the physical design data stored in the memory, and, as a result of the determination, in a case where the distance between the sequential circuit to be added and the first buffer is between the maximum value and the minimum value, the processor performs wiring processing of the clock signal supplied from the first buffer for the sequential circuit to be added.

Abstract: A design support device includes placement determination unit, logic extraction unit, and logic placement unit. The placement determination unit performs the process of determining the optimum position of a first terminal of a first cell as a first position in which the inter-terminal wiring between the first cell and a second cell connected to the first cell through the first terminal is short. Furthermore, the logic placement unit performs the process of extracting one or more logical blocks including a logical block having the first terminal from the first cell, and arranging one or more logical blocks so that the first terminal may become close to the first position.

Abstract: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Abstract: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Abstract: A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.

Abstract: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Abstract: A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.

Abstract: A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.

Abstract: A delay library generation device includes a grouping unit that generates a group including an output terminal of a sequential logic circuit and an input terminal of the sequential logic circuit that influences the output terminal based on circuit information of the sequential logic circuit, a signal pattern generation unit that generates a signal pattern set for the input terminal of the sequential logic circuit for each generated group based on a true value table of the sequential logic circuit and a library generation unit that measures a delay of the sequential logic circuit for each group and generates a delay library of the sequential logic circuit based on the measured delay.

Abstract: A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.

Abstract: A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.

Abstract: A circuit analyzing device includes: a peripheral input signal setting part configured to make a signal setting by a predetermined requirement for a peripheral input which does not logically affect operation of the predetermined circuit part, upon analyzing a signal delay in operation of a predetermined circuit part, and wherein: analysis is made for a signal propagation operation delay in operation of the predetermined circuit part, in consideration of influence of the signal input from the signal setting.

Abstract: A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.

Abstract: A circuit analyzing device includes: a peripheral input signal setting part configured to make a signal setting by a predetermined requirement for a peripheral input which does not logically affect operation of the predetermined circuit part, upon analyzing a signal delay in operation of a predetermined circuit part, and wherein: analysis is made for a signal propagation operation delay in operation of the predetermined circuit part, in consideration of influence of the signal input from the signal setting.

Abstract: An activation path simulation equipment and an activation path simulation method in accordance with the present invention divides a transistor circuit into a plurality of blocks with reference to pn junction nodes of the transistors included therein, and activation patterns are determined for each block using the characteristics of each transistor so as to efficiently create activation patterns of the transistor circuit. In this way, the number of activation patterns to be created can be decreased without creating unnecessary activation patterns, therefore the number of times of simulation can be decreased, which means that simulation speed increases.