Abstract: A light emitting element includes a semiconductor laminate structure including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type, a part of the second semiconductor layer and the light emitting layer being removed to expose a part of the first semiconductor layer: a first reflecting layer on the semiconductor laminate structure and including an opening, the opening being formed in the exposed part of the first semiconductor layer, a transparent wiring electrode for carrier injection into the first semiconductor layer or the second semiconductor layer through the opening, a second reflecting layer formed on the transparent wiring electrode and covering a part of the opening so as to reflect light emitted from the light emitting layer and passing through the opening back to the first semiconductor layer.

Abstract: A first intermediate electrode 30 is a plural number of electrodes connecting to plural electrode forming parts formed in plural places, respectively on the surface of a first semiconductor layer 104. A second intermediate electrode 40 is a plural number of electrodes connecting to plural places of a transparent electrically conductive film 10, respectively. A first electrode 60 connects a plural number of the first intermediate electrodes 30 to each other, and a second electrode 70 connects a plural number of the second intermediate electrodes 40 to each other. The transparent electrically conductive film 10 is formed thin in a region A where a distance between the first intermediate electrode and the second intermediate electrode is the shortest, as compared with other regions.

Abstract: A semiconductor light-emitting element includes a semiconductor laminated structure including a light-emitting layer sandwiched between first and second conductivity type layers for extracting an emitted light from the light-emitting layer on a side of the second conductivity type layer, a transparent electrode in ohmic contact with the second conductivity type layer, an insulation layer formed on the transparent electrode, an upper electrode for wire bonding formed on the insulation layer, a lower electrode that penetrates the insulation layer, is in ohmic contact with the transparent electrode and the electrode for wire bonding, and has an area smaller than that of the upper electrode in top view, and a reflective portion for reflecting at least a portion of light transmitted through a region of the transparent electrode not in contact with the lower electrode.

Abstract: A method for forming a film of silane coupling agent on a metal surface is provided. The method includes: a step of applying a solution containing a silane coupling agent on the metal surface; a step of drying the metal surface coated with the solution at a temperature in the range of 25 to 150° C. and for a length of time of 5 minutes or less; and a step of water-rinsing the dried metal surface.

Abstract: An adhesive layer for resin according to the present invention is formed of copper or a copper alloy for adhering a resin to a layer of copper or a copper alloy. The adhesive layer is formed of a metal layer of a coralloid structure made of an aggregation of a number of particles of copper or a copper alloy with gaps between the particles, and a plurality of micropores are present on the surface. The micropores have an average diameter in a range of 10 nm to 200 nm, and at least two micropores in average are present per 1 ?m2 of the metal layer surface. Thereby, sufficient adhesion between the resin and the copper or copper alloy is provided. This serves to prevent ion migration caused by dendrites, which has been a problem in a conventional layer of tin or a tin alloy, and the adhesion to a resin having a high-glass transition temperature (Tg) is improved as well. The present invention also provides a method of producing a laminate including the adhesive layer.

Abstract: A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.

Abstract: A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.

Abstract: The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.

Abstract: Disclosed is a data processing apparatus comprising a decode device for decoding an instruction code including an operation code and two register designation codes and an instruction execution device for executing appropriate process according to the results decoded by the decode device, wherein the instruction execution device executes a first process when the two register designation codes are different from each other and executes a second process when they are equal.

Abstract: A microprocessor which reduces power consumption by monitoring the operating status of a plurality of operating units in the microprocessor to extract the unit which is recently most infrequently used to change the frequency of the operating clock supplied thereto in steps.

Abstract: An instruction fetching device includes one or both of a cache device and a branch history table. The cache device stores a plurality of pairs, each pair including an instruction string divided into minimum unit instructions and an address of the instruction string. At the time of reading an instruction, an instruction string is selected and output by every minimum unit instruction from at least two pairs. The branch history table stores a plurality of pairs, each pair including a branch destination address and a set of an address of a branch instruction and a value obtained by subtracting a given value from the address.

Abstract: A central processing unit includes an instruction decoder (1), an operand address computation unit (2), an operand pre-fetch unit (3), a control information buffer (5), an arithmetic unit (4), an instruction fetch unit (6), a chip bus (7), and a bus controller (8). A process relating to the fetch of a memory operand is independent from main pipeline process having an instruction fetching stage, an instruction decoding stage, and an instruction execution stage. As a result, control information (13) in an instruction that the fetch of the memory operand is not required does not pass through the pipeline stage relating to the fetch of the memory operand thereby improving bus band width for memory operand accesses.