Patents by Inventor Masashi Hayano

Masashi Hayano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240020154
    Abstract: A device includes a processor configured to: classify arithmetic processing devices that executes tasks in parallel by distributing loads into arithmetic processing device groups; select a representative arithmetic processing device; notify the representative arithmetic processing device of identification information of other arithmetic processing devices of an arithmetic processing device group to which the representative arithmetic processing device belongs; instruct the representative arithmetic processing device to acquire information regarding tasks to be executed by the arithmetic processing devices of the arithmetic processing device group from a first task list, and to generate a second task list; notify each other arithmetic processing devices of identification information of the representative arithmetic processing device; and instruct each other arithmetic processing device to acquire information regarding tasks to be executed by the representative arithmetic processing device and each other arithm
    Type: Application
    Filed: April 28, 2023
    Publication date: January 18, 2024
    Applicant: Fujitsu Limited
    Inventors: Masashi HAYANO, Takumi HONDA, Naoto FUKUMOTO
  • Publication number: 20230259365
    Abstract: A recording medium stores a program for causing a computer to execute process including: incrementing a counter when a CISC instruction is converted into a RISC instruction; updating conversion timing of a register used for conversion with a value of the counter; recording a difference before and after update of conversion timing as an interval; selecting a register number from among register numbers that have a same interval condition, and updating the use register number with a selected register number; saving data for a register indicated by the updated use register number and generating an instruction for reading data of a memory operand; when a CISC instruction before conversion does not include the use register number, generating an instruction for reading data of a memory operand without restoring and saving data for a register indicated by the use register number; and generating the RISC instruction equivalent to the CISC instruction.
    Type: Application
    Filed: November 9, 2022
    Publication date: August 17, 2023
    Applicant: Fujitsu Limited
    Inventors: Masashi Hayano, Takumi Honda
  • Patent number: 6343082
    Abstract: A voice band signal is compression-encoded at a voice compression-encoding portion and is assembled into a cell at a cell assembling portion. Conversely, the voice band signal is disassembled at a cell disassembling portion and is decoded at a voice compression-decoding portion. When, from both of up and down data judging portions, receiving a judgement of coincidence of the voice band signal with a signal at the time when the line is unused, a timer counts a continuation time. When the continuation time exceeds a protection time, a protection time judging portion causes the cell assembling portion to stop the cell transmission. When, from either of the up and down data judging portions, receiving a judgement of no coincidence with the signal at the time when the line is unused, or when the continuation time does not exceed the protection time, the cell assembling portion is directed to transmit the cell.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: January 29, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetoshi Fuse, Masashi Hayano, Toshiya Suganuma, Takeshi Kawanobe