Abstract: An information processing circuitry includes a storage data generation circuitry, a storage circuitry, a comparison data generation circuitry, and a data comparison circuitry. The storage data generation circuitry is configured to add redundancy bits and a write flag indicating that writing has been made, to input data to generate storage data. The storage circuitry is configured to store the storage data. The comparison data generation circuitry is configured to generate redundancy bits from data stored in the storage circuitry and address accessing to the storage circuitry. The data comparison circuitry is configured to compare the redundancy bits added by the storage data generation circuitry with the redundancy bits generated by the comparison data generation circuitry to execute error detection based on a comparison result and on the write flag.

Abstract: An information processing circuitry includes a storage data generation circuitry, a storage circuitry, a comparison data generation circuitry, and a data comparison circuitry. The storage data generation circuitry is configured to add redundancy bits and a write flag indicating that writing has been made, to input data to generate storage data. The storage circuitry is configured to store the storage data. The comparison data generation circuitry is configured to generate redundancy bits from data stored in the storage circuitry and address accessing to the storage circuitry. The data comparison circuitry is configured to compare the redundancy bits added by the storage data generation circuitry with the redundancy bits generated by the comparison data generation circuitry to execute error detection based on a comparison result and on the write flag.

Abstract: A data transfer circuit including: a measurement circuit that measures a transfer time of transfer data; a data processing circuit that is connected to the measurement circuit, and that, when the transfer time exceeds a threshold, performs lossy compression to reduce a data volume; and a control circuit that is connected to the data processing circuit, and that performs control to transfer data.

Abstract: An image processing apparatus according to an embodiment has: a first pseudo random number generator configured to generate a pseudo random number and write the pseudo random number into a first memory; a processing circuit configured to read out the random number from the first memory, execute specific processing on the random number, and write a processing result of the specific processing into a second memory; a first signature generator configured to read out the processing result from the second memory, and generate a signature based on the processing result; and a first signature comparator configured to compare the signature generated by the first signature generator and a first expected value, the first expected value being an expected value of a signature based on the random number generated by the first pseudo random number generator and based on processing contents of the processing circuit.

Abstract: A data transfer circuit including: a measurement circuit that measures a transfer time of transfer data; a data processing circuit that is connected to the measurement circuit, and that, when the transfer time exceeds a threshold, performs lossy compression to reduce a data volume; and a control circuit that is connected to the data processing circuit, and that performs control to transfer data.

Abstract: According to one embodiment, an image processing apparatus includes an encoding unit that compresses an input image for each pixel block having a size smaller than a line to generate a plurality of compressed blocks, and store the compressed blocks in a frame buffer, a reading unit that identifies an object block to be expanded among the compressed blocks, and reads the object block from the frame buffer, a decoding unit that expands the object block to generate an expanded block, and an information acquiring unit that acquires, based on the expanded block, position information used by the reading unit to identify the block to be expanded, or decode information used by the decoding unit to expand another compressed block.

Abstract: With a video compression device configured to compress one pixel per cycle, a predictive pixel generation unit generates predictive pixel values of a plurality of predictive modes defined assuming local decode pixels read from predetermined positions of a line memory as upper reference pixels and an input original image pixel positioned on the left side of a pixel to be compressed as a left reference pixel for the pixel to be compressed. A predictive mode determination unit calculates a predictive error in a unit based on differential values between the pixel value to be compressed and the predictive pixel value, and selects a minimum predictive mode. A DPCM unit generates a minimum differential value between the minimum predictive pixel value and the pixel to be compressed assuming local decode pixels as upper reference pixels and a local decode pixel value one cycle before as a left reference pixel.

Abstract: According to one embodiment, an image processing apparatus includes an encoding unit that compresses an input image for each pixel block having a size smaller than a line to generate a plurality of compressed blocks, and store the compressed blocks in a frame buffer, a reading unit that identifies an object block to be expanded among the compressedblocks, and reads the object block from the frame buffer, a decoding unit that expands the object block to generate an expanded block, and an information acquiring unit that acquires, based on the expanded block, position information used by the reading unit to identify the block to be expanded, or decode information used by the decoding unit to expand another compressed block.

Abstract: With a video compression device configured to compress one pixel per cycle, a predictive pixel generation unit generates predictive pixel values of a plurality of predictive modes defined assuming local decode pixels read from predetermined positions of a line memory as upper reference pixels and an input original image pixel positioned on the left side of a pixel to be compressed as a left reference pixel for the pixel to be compressed. A predictive mode determination unit calculates a predictive error in a unit based on differential values between the pixel value to be compressed and the predictive pixel value, and selects a minimum predictive mode. A DPCM unit generates a minimum differential value between the minimum predictive pixel value and the pixel to be compressed assuming local decode pixels as upper reference pixels and a local decode pixel value one cycle before as a left reference pixel.

Abstract: According to an embodiment, an image encoding device includes a deciding unit, an assigning unit, and an encoding unit. The deciding unit is configured to determine representative colors for expressing each of pixel blocks into which image data are divided. The assigning unit is configured to assign an index for identifying the representative color to each pixel in the pixel block. The encoding unit is configured to encode indices and the representative colors, the indices and the representative colors in each pixel box being arranged alternately so that two representative colors are discontinuously encoded.

Abstract: A variable-length code decoding apparatus has a first-table storing part to store a first table, a second-table storing part to store a second table, a priority determining part to read out by priority a combination of zero information that is stored in the second table and corresponds a combination of variable-length codes having the largest number of codes, whereas if variable-length codes included in the input bitstream is not stored in the second table but stored in the first table, to read out zero information, and a decoding part to generate the decoded data based on the zero information or the combination of zero information read out by the priority determining part.

Abstract: A variable-length code decoding apparatus has a first-table storing part to store a first table, a second-table storing part to store a second table, a priority determining part to read out by priority a combination of zero information that is stored in the second table and corresponds a combination of variable-length codes having the largest number of codes, whereas if variable-length codes included in the input bitstream is not stored in the second table but stored in the first table, to read out zero information, and a decoding part to generate the decoded data based on the zero information or the combination of zero information read out by the priority determining part.

Abstract: The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.

Abstract: A digital camera that is an image pickup device includes: a sensor; a background portion movement speed calculating unit configured to calculate a movement speed of a background portion of a subject from a plurality of images picked up by the sensor; and a shutter speed calculating unit configured to calculate a shutter speed from the movement speed and a predetermined image flow quantity.

Abstract: An image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix, a suffix, and a syntax; a variable length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length, and, by using data contained in the bit stream and the suffix length, simultaneously decode the prefix and the suffix and output the result if the syntax selection signal selects the prefix 1 and the suffix, and decode the syntax and output the result if the syntax selection signal selects the syntax; a level formation device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and update the suffix length.

Abstract: An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

Abstract: When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.

Abstract: An encoding apparatus includes: an orthogonal transformation unit configured to orthogonally transform image data of a predetermined block size; a binarization unit configured to binarize the image data outputted from the orthogonal transformation unit; an arithmetic encoding unit configured to arithmetically encode the binary data generated by the binarization unit; and a prediction unit configured to predict, from the binary data, whether or not the amount of arithmetically encoded data generated by the arithmetic encoding unit exceeds a permissible maximum code amount based on a predetermined encoding standard. The encoding apparatus performs, when the prediction result is that the amount of arithmetically encoded data exceeds the maximum code amount, control to prevent the arithmetic encoding by the arithmetic encoding unit from being performed to the binary data corresponding to the prediction result.

Abstract: An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

Abstract: According to the present invention, there is provided an image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to recei