Patents by Inventor Masashi Matsumura
Masashi Matsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936500Abstract: An in-vehicle network system deployed in a vehicle includes a plurality of first nodes configured to perform an operation relevant to a first function in the vehicle, a second node configured to perform an operation relevant to a second function different from the first function in the vehicle; and a relay device configured to relay communication between the first nodes and the second node. The relay device is configured to start relay of communication between the first nodes earlier than the relay of communication between the first node and the second node at a time of startup.Type: GrantFiled: December 29, 2020Date of Patent: March 19, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shu Ishizuka, Hiroya Ando, Taichi Matsumura, Masashi Amesara, Yutaka Ueda, Toshio Kawamura, Tomomi Kawamura, Yoshifumi Ohmori, Toshio Shimada, Yoshiro Hirata
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Patent number: 8837238Abstract: A semiconductor device which can reduce the peak value of the rush current generated during a transition from resume mode to normal mode. The semiconductor device has a plurality of daisy-chained memory modules. Each of the memory modules includes a memory array, a switch for controlling, in resume mode, source voltage supply to a constituent element of the memory module, and a delay circuit which receives a resume control signal ordering a transition from resume mode to normal mode and outputs a resume control signal delayed from the inputted resume control signal to the memory module of the next stage.Type: GrantFiled: January 6, 2012Date of Patent: September 16, 2014Assignee: Renesas Electronics CorporationInventors: Masashi Matsumura, Hiroyuki Motomura
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Patent number: 8599639Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: GrantFiled: May 22, 2013Date of Patent: December 3, 2013Assignee: Renesas Electronics CorporationInventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Publication number: 20130249624Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: ApplicationFiled: May 22, 2013Publication date: September 26, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Mihoko AKIYAMA, Futoshi IGAUE, Kenji YOSHINAGA, Masashi MATSUMURA, Fukashi MORISHITA
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Patent number: 8451678Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: GrantFiled: April 5, 2011Date of Patent: May 28, 2013Assignee: Renesas Electronics CorporationInventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Publication number: 20120185687Abstract: A semiconductor device which can reduce the peak value of the rush current generated during a transition from resume mode to normal mode. The semiconductor device has a plurality of daisy-chained memory modules. Each of the memory modules includes a memory array, a switch for controlling, in resume mode, source voltage supply to a constituent element of the memory module, and a delay circuit which receives a resume control signal ordering a transition from resume mode to normal mode and outputs a resume control signal delayed from the inputted resume control signal to the memory module of the next stage.Type: ApplicationFiled: January 6, 2012Publication date: July 19, 2012Inventors: Masashi MATSUMURA, Hiroyuki Motomura
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Patent number: 8004923Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: GrantFiled: January 7, 2010Date of Patent: August 23, 2011Assignee: Renesas Electronics CorporationInventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Publication number: 20110182131Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: ApplicationFiled: April 5, 2011Publication date: July 28, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Publication number: 20100109761Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Applicant: Renesas Technology Corp.Inventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Patent number: 7656736Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: GrantFiled: March 14, 2007Date of Patent: February 2, 2010Assignee: Renesas Technology Corp.Inventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Publication number: 20080298156Abstract: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.Type: ApplicationFiled: July 9, 2008Publication date: December 4, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kenji YOSHINAGA, Masashi Matsumura, Futoshi Igaue, Mihoko Akiyama, Fukashi Morishita
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Patent number: 7408818Abstract: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.Type: GrantFiled: February 8, 2007Date of Patent: August 5, 2008Assignee: Renesas Technology Corp.Inventors: Kenji Yoshinaga, Masashi Matsumura, Futoshi Igaue, Mihoko Akiyama, Fukashi Morishita
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Publication number: 20070216467Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: ApplicationFiled: March 14, 2007Publication date: September 20, 2007Inventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Publication number: 20070183214Abstract: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.Type: ApplicationFiled: February 8, 2007Publication date: August 9, 2007Inventors: Kenji Yoshinaga, Masashi Matsumura, Futoshi Igaue, Mihoko Akiyama, Fukashi Morishita
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Patent number: 5991232Abstract: A semiconductor integrated circuit device includes an SDRAM module operating in synchronization with a clock signal, a logic circuit transmitting data with the SDRAM module for effecting necessary processing, a direct memory access circuit taking in and transferring an externally applied signal in synchronization with the clock signal corresponding to an operation clock of the SDRAM module, and a selector selecting either the output signal of the logic circuit and the output signal of the direct memory access circuit in accordance with a test mode instructing signal for application to the SDRAM module. A test of a synchronous memory can be performed by externally making fast and direct access to the synchronous memory without an influence of a skew in a signal.Type: GrantFiled: August 28, 1998Date of Patent: November 23, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Masashi Matsumura, Akira Yamazaki, Isamu Hayashi, Atsuo Mangyo
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Patent number: 5930194Abstract: Columns included in a sub-block are divided into first and second groups. If a defective memory cell column is present in the first group, an address comparison circuit activates a signal to select a redundant memory cell column, then selection prohibiting signal attains an "L" level based on information programmed in a programming circuit, a selection of a column in the first group is prohibited, and a redundant memory cell column selection signal is activated. Meanwhile, a normal selecting operation is performed to the second column group.Type: GrantFiled: July 2, 1998Date of Patent: July 27, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Tadato Yamagata, Akira Yamazaki, Shigeki Tomishima, Makoto Hatakenaka, Masashi Matsumura
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Patent number: 5519677Abstract: An objective lens driving biaxial actuator for driving an objective lens in both a focusing direction and a tracking direction with respect to a recording medium. The biaxial actuator comprises: a movable portion for holding the objective lens; an elastic member having its one end attached to the movable portion for movably supporting the movable portion; a stationary portion fixing the other end of the elastic member; and a balancer disposed at the side of the stationary portion with respect to the objective lens and carried on the movable portion at such a distance that its clearance from the stationary portion may restrict the deformation of the elastic member within an elastic limit. A hinge is interposed between the elastic member and the movable portion for moving the objective lens in the tracking direction.Type: GrantFiled: March 18, 1994Date of Patent: May 21, 1996Assignee: Sony CorporationInventors: Keiichi Shibata, Takatoshi Hirata, Masashi Matsumura