Patents by Inventor Masashi Norimoto

Masashi Norimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7338904
    Abstract: A surface of a semiconductor wafer which has been lapped is ground. This removes a damage caused on the wafer surface during lapping, thereby increasing the flatness of the wafer surface. Next, the wafer is subjected to composite etching and the both surfaces are polished, i.e., subjected to mirror polishing while the wafer rear surface is slightly polished so as to obtain a single-side mirror surface wafer having a difference between the front and the rear surfaces. As compared to mere acid etching or alkali etching, it is possible to manufacture a single-side mirror surface wafer having a higher flatness.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 4, 2008
    Assignee: SUMCO Corporation
    Inventors: Sakae Koyata, Tadashi Denda, Masashi Norimoto, Kazushige Takaishi
  • Publication number: 20070158308
    Abstract: A surface of a semiconductor wafer which has been lapped is ground. This removes a damage caused on the wafer surface during lapping, thereby increasing the flatness of the wafer surface. Next, the wafer is subjected to composite etching and the both surfaces are polished, i.e., subjected to mirror polishing while the wafer rear surface is slightly polished so as to obtain a single-side mirror surface wafer having a difference between the front and the rear surfaces. As compared to mere acid etching or alkali etching, it is possible to manufacture a single-side mirror surface wafer having a higher flatness.
    Type: Application
    Filed: December 3, 2004
    Publication date: July 12, 2007
    Applicant: SUMCO CORPORATION
    Inventors: Sakae Koyata, Tadashi Denda, Masashi Norimoto, Kazushige Takaishi
  • Patent number: 7226864
    Abstract: Provided is an improved method for producing a silicon wafer whose surfaces exhibit precise flatness and minute surface roughness, and which allows one to visually discriminate between the front and rear surfaces, the method comprising a slicing step of slicing a single-crystal ingot into thin disc-like wafers, a chamfering step of chamfering the wafer, a lapping step for flattening the wafer, an etching step for removing processing distortions on the wafer surfaces, a mirror-polishing step for mirror-polishing the surface of the wafer, and a cleaning step for cleaning the wafer. The etching step further comprises a first acid-etching phase and a second alkali-etching phase, and a rear surface mild polishing step is introduced between the first and second etching phases in order to abrade part of roughness formed on the rear surface of the wafer as a result of the first etching phase.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: June 5, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi, Tohru Taniguchi, Kazuo Fujimaki, Akihiro Kudo, Masashi Norimoto
  • Publication number: 20060194441
    Abstract: The invention is improvement of a silicon wafer etching method of storing an acid etching solution and an alkali etching solution respectively in plural etching tanks, and immersing a silicon wafer having a work-degenerated layer, which has experienced a lapping process and then a cleaning process, in the acid etching solution and the alkali etching solution in order. Its characteristic configuration is in that an alkali etching process is performed after an acid etching process, the etching removal depth for acid etching is made to be equal to or larger than the etching removal depth for alkali etching, and the etching rate of acid etching is made to be 0.0075 ?m/sec to 0.05 ?m/sec in total of the obverse and the reverse of the silicon wafer.
    Type: Application
    Filed: February 25, 2005
    Publication date: August 31, 2006
    Inventors: Sakae Koyata, Kazushige Takaishi, Masashi Norimoto
  • Publication number: 20050112893
    Abstract: Provided is an improved method for producing a silicon wafer whose surfaces exhibit precise flatness and minute surface roughness, and which allows one to visually discriminate between the front and rear surfaces, the method comprising a slicing step of slicing a single-crystal ingot into thin disc-like wafers, a chamfering step of chamfering the wafer, a lapping step for flattening the wafer, an etching step for removing processing distortions on the wafer surfaces, a mirror-polishing step for mirror-polishing the surface of the wafer, and a cleaning step for cleaning the wafer. The etching step further comprises a first acid-etching phase and a second alkali-etching phase, and a rear surface mild polishing step is introduced between the first and second etching phases in order to abrade part of roughness formed on the rear surface of the wafer as a result of the first etching phase.
    Type: Application
    Filed: October 1, 2004
    Publication date: May 26, 2005
    Inventors: Sakae Koyata, Kazushige Takaishi, Tohru Taniguchi, Kazuo Fujimaki, Akihiro Kudo, Masashi Norimoto