Patents by Inventor Masashi Ogita

Masashi Ogita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing interconnect metallization comprising metal nitride and silicide
    Patent number: 5312772
    Abstract: In a semiconductor device including a substrate of Si or polycrystalline silicon and an interlayer insulation film region, a region for interconnection with the substrate is composed of a refractory metal silicide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, while a region for interconnection on the interlayer insulation film on the substrate is composed of a refractory metal, or refractory metal oxide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, providing interconnections for integrated circuits. In the manufacture of this interconnection structure, rapid thermal annealing is performed at 600.degree.-1000.degree. C. on the refractory metal nitride layer of the region for interconnection with the substrate, followed by the formation of Al or Al alloy layer.
    Type: Grant
    Filed: April 1, 1992
    Date of Patent: May 17, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Yokoyama, Juri Kato, Masashi Ogita
  • Ohmic contact to silicon substrate
    Patent number: 4998157
    Abstract: In a semiconductor device including a substrate of Si or polycrystalline silicon and an interlayer insulation film region, a region for interconnection with the substrate is composed of a refractory metal silicide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, while a region for interconnection on the interlayer insulation film on the substrate is composed of a refractory metal, or refractory metal oxide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, providing interconnections for integrated circuits. In the manufacture of this interconnection structure, rapid thermal annealing is performed at 600.degree.-1000.degree. C. on the refractory metal nitride layer of the region for interconnection with the substrate, followed by the formation of Al or Al alloy layer.
    Type: Grant
    Filed: August 1, 1989
    Date of Patent: March 5, 1991
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Yokoyama, Juri Kato, Masashi Ogita