Patents by Inventor Masashi Sakai
Masashi Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240407094Abstract: A printed wiring board includes a conductor layer including wirings, a resin insulating layer having openings, a mounting conductor layer including first and second electrodes, first via conductors including a seed layer and an electrolytic plating layer such that the first via conductors connect the first electrodes and the wirings, and second via conductors including the seed layer and electrolytic plating layer such that the second via conductors connect the second electrodes and the wirings. The first electrodes are positioned to mount a first electronic component. The second electrodes are positioned to mount a second electronic component. The first and second via conductors are formed such that the seed layer is covering an inner wall surface of each opening in the insulating layer and has a first portion and a second portion connected to the first portion and having a part of the first portion formed on the second portion.Type: ApplicationFiled: May 31, 2024Publication date: December 5, 2024Applicant: IBIDEN CO., LTD.Inventors: Masashi KUWABARA, Susumu KAGOHASHI, Jun SAKAI, Takuya INISHI, Kyohei YOSHIKAWA
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Publication number: 20240389231Abstract: A printed wiring board includes a mounting conductor layer including first and second electrodes, a connection conductor layer including connection wirings such that the connection wirings connect the first and second electrodes, a resin insulating layer formed between the mounting conductor layer and the connection conductor layer and having openings, and connection via conductors formed in the openings of the resin insulating layer and including first and second connection via conductors such that the first connection via conductors electrically connect the first electrodes and the connection wirings and the second connection via conductors electrically connect the second electrodes and the connection wirings. The resin insulating layer includes inorganic particles and resin. The inorganic particles include first inorganic particles forming inner wall surfaces in the openings and second inorganic particles embedded in the resin insulating layer.Type: ApplicationFiled: May 10, 2024Publication date: November 21, 2024Applicant: IBIDEN CO., LTD.Inventors: Masashi KUWABARA, Jun SAKAI, Takuya INISHI
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Publication number: 20240363541Abstract: A wiring substrate includes a first build-up part including first insulating layers, first conductor layers, and first via conductors, and a second build-up part including second insulating layers and second conductor layers. The minimum wiring width and minimum inter-wiring distance in the first conductor layers are smaller than the minimum wiring width and minimum inter-wiring distance in the second conductor layers. The first conductor layers and via conductors include a first layer and a second layer formed on the first layer. The first layer includes a lower layer including a sputtering film including an alloy including copper, aluminum, and at least one element selected from nickel, zinc, gallium, silicon, and magnesium, and an upper layer including a sputtering film including copper. The lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors.Type: ApplicationFiled: April 26, 2024Publication date: October 31, 2024Applicant: IBIDEN CO., LTD.Inventors: Masashi KUWABARA, Susumu KAGOHASHI, Jun SAKAI, Kyohei YOSHIKAWA
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Publication number: 20240365468Abstract: A wiring substrate includes a first build-up part including an insulating layer and a conductor layer, and a second build-up part laminated on the first build-up part and including an insulating layer and a conductor layer. The minimum width and minimum inter-wiring distance of wirings in the first build-up part are smaller than the minimum width and minimum inter-wiring distance of wirings in the second build-up part. The insulating layer in the first build-up part includes resin and inorganic particles including first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin such that the first inorganic particles have first portions protruding from the resin and second portions embedded in the resin, respectively. The insulating layer of the first build-up part has a surface covered by the conductor layer and including a surface of the resin and exposed surfaces of the first portions.Type: ApplicationFiled: April 23, 2024Publication date: October 31, 2024Applicant: IBIDEN CO., LTD.Inventors: Masashi KUWABARA, Susumu KAGOHASHI, Jun SAKAI, Kyohei YOSHIKAWA
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Patent number: 12125969Abstract: A halide solid electrolyte material according to the present disclosure is represented by the chemical formula Li6-4b+2ab(Zr1-aMa)bX6 (I), wherein M denotes at least one element selected from the group consisting of Mg, Ca, Sr, Ba, and Zn, X denotes at least one halogen element, and two mathematical formulae 0<a<1 and 0<b<1.5 are satisfied.Type: GrantFiled: December 10, 2020Date of Patent: October 22, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Masashi Sakaida, Tetsuya Asano, Akihiro Sakai, Yusuke Nishio, Akinobu Miyazaki
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Publication number: 20240339388Abstract: A wiring substrate includes a first build-up part including an insulating layer and a conductor layer, and a second build-up part including an insulating layer and a conductor layer. The minimum wiring width of wirings in the conductor layer of the first build-up part is smaller than the minimum wiring width of wirings in the conductor layer of the second build-up part. The minimum inter-wiring distance of the wirings in the first part is smaller than the minimum inter-wiring distance of the wirings in the second part. The first build-up part is formed such that the conductor layer includes a conductor pattern including a first metal layer, a second metal layer, and a third metal layer. The width of the first metal layer is larger than the width of the second metal layer. The width of the third metal layer is larger than the width of the first metal layer.Type: ApplicationFiled: April 4, 2024Publication date: October 10, 2024Applicant: IBIDEN CO., LTD.Inventors: Masashi KUWABARA, Jun SAKAI, Shiho SHIMADA
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Publication number: 20240337604Abstract: An appearance inspection apparatus includes a shape measurement unit configured to measure the three-dimensional shape of a weld and a data processor configured to process shape data acquired by the shape measurement unit. The data processor includes a shape data processor configured to correct a resolution of the shape data, a learning data set generator configured to generate a plurality of learning data sets by performing data augmentation on multiple pieces of sample shape data acquired in advance, a determination model generator configured to generate a determination model using the plurality of learning data sets, and a first determination unit configured to determine whether the shape of the weld is good or bad based on the shape data having the corrected resolution and the determination model.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Inventors: Toru SAKAI, Masashi YOSHIDA, Michio SAKURAI, Daichi HIGASHI
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Publication number: 20240324103Abstract: A wiring substrate includes a core substrate including a through-hole conductor, a first resin insulating layer, a first conductor layer including a seed layer and an electrolytic plating layer, a via conductor formed such that the via conductor electrically connects the through-hole conductor and first conductor layer, and a second resin insulating layer covering the first conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is penetrating through the glass substrate, the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, and the first conductor layer includes a conductor circuit such that a width of the first layer is larger than a width of the second layer in the conductor circuit and a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit.Type: ApplicationFiled: March 22, 2024Publication date: September 26, 2024Applicant: IBIDEN CO., LTD.Inventors: Masashi KUWABARA, Jun SAKAI, Shiho FUKUSHIMA
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Patent number: 12095027Abstract: Provided is a solid electrolyte material represented by the following composition formula (1): Li6-3dYdX6??Formula (1) where X is two or more kinds of elements selected from the group consisting of Cl, Br, and I; and 0<d<2.Type: GrantFiled: June 25, 2020Date of Patent: September 17, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Akihiro Sakai, Tetsuya Asano, Masashi Sakaida, Yusuke Nishio, Akinobu Miyazaki, Shinya Hasegawa
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Publication number: 20240306296Abstract: A wiring substrate includes a core substrate including a glass substrate and a through-hole conductor formed in the glass substrate, a resin insulating layer formed on the core substrate and including resin and inorganic particles, a conductor layer formed on the insulating layer and including a seed layer and an electrolytic plating layer, and a via conductor formed in the insulating layer such that the via conductor is electrically connected to the through-hole conductor formed in the glass substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The conductor layer and the via conductor are formed such that the seed layer is formed by sputtering, and the resin insulating layer has an opening in which the via conductor is formed such that the inorganic particles include first particles forming an inner wall surface in the opening and second particles embedded in the insulating layer.Type: ApplicationFiled: March 8, 2024Publication date: September 12, 2024Applicant: IBIDEN CO., LTD.Inventors: Toshiki FURUTANI, Masashi KUWABARA, Jun SAKAI, Takuya INISHI
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Patent number: 12074279Abstract: The present disclosure provides a solid electrolyte material having high lithium ion conductivity. The solid electrolyte material of the present disclosure includes Li, M and X. M is at least one element selected from the group consisting of Mg, Zn and Cd. X is at least two elements selected from the group consisting of Cl, Br and I.Type: GrantFiled: September 9, 2021Date of Patent: August 27, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Koki Ueno, Masashi Sakaida, Akihiro Sakai, Akinobu Miyazaki
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Publication number: 20240248361Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.Type: ApplicationFiled: March 4, 2024Publication date: July 25, 2024Applicant: Japan Display Inc.Inventors: Masashi TSUBUKU, Takeshi SAKAI, Tatsuya TODA
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Publication number: 20240243049Abstract: A wiring substrate includes a first build-up part including first insulating layers and conductor layers, a second build-up part laminated to the first part and including second insulating layers and conductor layers, and via conductors including first via conductors in the first insulating layers and second via conductors in the second insulating layers. The first part is positioned closer to first surface side of the substrate than the second part. The first conductor layers include wirings having wiring width and inter-wiring distance that are smaller than wiring width and inter-wiring distance of wirings in the second conductor layers. The first insulating layers include resin and inorganic particles including first particles forming inner wall surfaces in through holes and second particles embedded in the first insulating layers having different shapes from the first particles. Each first conductor layers and via conductors includes a metal film layer and a plating film layer.Type: ApplicationFiled: January 17, 2024Publication date: July 18, 2024Applicant: IBIDEN CO., LTD.Inventors: Toshiki FURUTANI, Masashi KUWABARA, Jun SAKAI, Takuya INISHI
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Publication number: 20240241078Abstract: An ion sensor includes an ion detection element, a reference electrode that provides a reference point of a potential, and a solution in which an ion concentration can be changed in a sensing area of the ion detection element. The sensing area of the ion detection element is disposed in the solution. A method for detecting a target substance employs an ion sensor. The target substance bound to a label having a function of changing the amount of ions detectable by the ion sensor is introduced into the solution, and a change in the amount of ions is detected using the ion sensor.Type: ApplicationFiled: March 13, 2024Publication date: July 18, 2024Inventors: Kazuhisa NAKAGAWA, Yuhei Shimizu, Daisuke Kobayashi, Masashi Suzuki, Akira Nukazuka, Teppei Sakai, Kei Hayakawa, Kazuhiko Kano, Mana Asano
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Publication number: 20240238236Abstract: The present invention provides a composition for regulating carbohydrate metabolism, the composition containing, as an active ingredient, an agent for controlling the amount of D-amino acid in the living body of a subject. Moreover, the present invention provides a method for assessing carbohydrate metabolism conditions of a subject by monitoring the amount of D-amino acid in the living body of the subject.Type: ApplicationFiled: May 19, 2022Publication date: July 18, 2024Applicants: KAGAMI INC., NATIONAL UNIVERSITY CORPORATION KANAZAWA UNIVERSITYInventors: Takashi WADA, Norihiko SAKAI, Yasunori IWATA, Yusuke NAKADE, Taku KOBAYASHI, Masashi MITA
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Patent number: 11948794Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.Type: GrantFiled: April 27, 2021Date of Patent: April 2, 2024Assignee: Mitsubishi Electric CorporationInventors: Masashi Sakai, Takuma Mizobe, Takuyo Nakamura
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Publication number: 20230253372Abstract: A semiconductor device includes a plurality of arms each including: a heat dissipation plate; a switching element; a metal terminal; and a sealing material, the metal terminals of the two specific arms adjacent to each other in the first direction has a first protruding portion which protrudes from a portion of the sealing material on one side in the second direction, the first protruding portion of one specific arm is arranged on a side closer to the other specific arm than a center portion in the first direction is, at the portion of the sealing material on the one side in the second direction, and the first protruding portion of the other specific arm is arranged on a side closer to the one specific arm than a center portion in the first direction is, at the portion of the sealing material on the one side in the second direction.Type: ApplicationFiled: August 22, 2022Publication date: August 10, 2023Inventors: Masashi SAKAI, Masakazu TANI
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Patent number: 11694948Abstract: This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.Type: GrantFiled: October 20, 2021Date of Patent: July 4, 2023Assignee: Mitsubishi Electric CorporationInventor: Masashi Sakai
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Publication number: 20220328384Abstract: This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.Type: ApplicationFiled: October 20, 2021Publication date: October 13, 2022Applicant: Mitsubishi Electric CorporationInventor: Masashi SAKAI
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Publication number: 20220028688Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.Type: ApplicationFiled: April 27, 2021Publication date: January 27, 2022Applicant: Mitsubishi Electric CorporationInventors: Masashi SAKAI, Takuma MIZOBE, Takuyo NAKAMURA