Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

Abstract: A semiconductor device includes a plurality of arms each including: a heat dissipation plate; a switching element; a metal terminal; and a sealing material, the metal terminals of the two specific arms adjacent to each other in the first direction has a first protruding portion which protrudes from a portion of the sealing material on one side in the second direction, the first protruding portion of one specific arm is arranged on a side closer to the other specific arm than a center portion in the first direction is, at the portion of the sealing material on the one side in the second direction, and the first protruding portion of the other specific arm is arranged on a side closer to the one specific arm than a center portion in the first direction is, at the portion of the sealing material on the one side in the second direction.

Abstract: This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.

Abstract: This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.

Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

Abstract: A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5×1014/cm3 or more and 2×1016/cm3 or less.

Abstract: Provided are a silicon carbide epitaxial growth device capable of fostering epitaxial growth on a silicon carbide substrate. Mounting a wafer holder loaded with a silicon carbide substrate and a tantalum carbide member to a turntable in a susceptor, and supplying a growth gas, a doping gas, and a carrier gas into the susceptor by heating by induction heating coils placed around the susceptor, thereby epitaxial growth is fostered, and stable and proper device characteristics are obtained, moreover, the yield in a manufacturing step of the silicon carbide epitaxial wafer is significantly improved.

Abstract: The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.

Abstract: A silicon carbide epitaxial wafer includes a silicon carbide substrate and silicon carbide epitaxial layers formed on the silicon carbide substrate. Each of the silicon carbide epitaxial layers has a triangular defect. The silicon carbide epitaxial layer each have a step inside the triangular defect in the surface morphology of the triangular defect.

Abstract: A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5×1014/cm3 or more and 2×1016/cm3 or less.

Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.

Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.

Abstract: The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.

Abstract: A power converter includes: a base conductor, an electrically heating member which is provided on the base conductor, a noise reduction capacitor of flat plate-shape in which via an insulator, a plurality of first electrodes and second electrodes are alternately layered, on one surface, the first electrode in an outermost layer is exposed and on another surface, the second electrode in an outermost layer is exposed, a relay conductor which is electrically connected to other members from the electrically heating member via the noise reduction capacitor, and the second electrode in an outermost layer of the noise reduction capacitor is face-joined to a face of the base conductor at a side where the electrically heating member is provided and the first electrode in an outermost layer and the relay conductor are face-joined.

Abstract: A power converter includes: a base conductor, an electrically heating member which is provided on the base conductor, a noise reduction capacitor of flat plate-shape in which via an insulator, a plurality of first electrodes and second electrodes are alternately layered, on one surface, the first electrode in an outermost layer is exposed and on another surface, the second electrode in an outermost layer is exposed, a relay conductor which is electrically connected to other members from the electrically heating member via the noise reduction capacitor, and the second electrode in an outermost layer of the noise reduction capacitor is face-joined to a face of the base conductor at a side where the electrically heating member is provided and the first electrode in an outermost layer and the relay conductor are face-joined.

Abstract: A manufacturing method for manufacturing a silicon carbide epitaxial wafer includes: introducing a cleaning gas into a growth furnace to remove dendrite-like polycrystal of silicon carbide attached to an inner wall of the growth furnace; after introducing the cleaning gas, bringing a silicon carbide substrate in the growth furnace; and growing a silicon carbide epitaxial layer on the silicon carbide substrate by introducing a processing gas into the growth furnace to manufacture a silicon carbide epitaxial wafer, wherein the cleaning gas having fluid energy of 1.6E?4 [J] or higher is introduced into the growth furnace.

Abstract: A manufacturing method for manufacturing a silicon carbide epitaxial wafer includes: introducing a cleaning gas into a growth furnace to remove dendrite-like polycrystal of silicon carbide attached to an inner wall of the growth furnace; after introducing the cleaning gas, bringing a silicon carbide substrate in the growth furnace; and growing a silicon carbide epitaxial layer on the silicon carbide substrate by introducing a processing gas into the growth furnace to manufacture a silicon carbide epitaxial wafer, wherein the cleaning gas having fluid energy of 1.6E-4 [J] or higher is introduced into the growth furnace.

Abstract: The present invention relates to a laminated structure for realizing an arbitrary hollow structure by laminating in a predetermined order a plurality of plate-like members formed by punching in an arbitrary configuration. The plurality of plate-like members have a plurality of identification structure portions for individually identifying the plate-like members, and the plurality of identification structure portions are on the same side surface of a laminated structure thus obtained.

Abstract: Provided is a radio communication apparatus using a battery as a power supply, in which standby electricity is reduced to achieve a reduction in power consumption. The radio communication apparatus includes a time measuring unit (210) and a plurality of time signal outputting units (220 to 22n) such that a plurality of circuit blocks are intermittently operated for a minimum period of time, only a necessary circuit block is intermittently operated, or an intermittent operation is performed with a minimum power supplied, at desired independent time intervals or after desired independent elapsed time.

Abstract: A method for producing a phospholipid using transphosphatidylation, which comprises homogenizing a mixture of a raw material phospholipid, a hydroxyl-containing acceptor, phospholipase D, and water in the absence of an organic solvent to obtain a homogenized mixture; and subjecting the homogenized mixture to a transphosphatidylation reaction at 15° C. to 65° C. The homogenized mixture has a lamellar lyotropic liquid crystal structure. An objective phospholipid can be obtained from the homogenized mixture through transphosphatidylation without using an organic solvent or calcium.