Patents by Inventor Masashi Sakai

Masashi Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113546
    Abstract: A semiconductor device includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, and a gate insulating layer between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes a source region and a drain region each containing an impurity element, a channel region between the source region and the drain region, and a first region adjacent to the channel region. The first region includes a first edge extending along a first direction travelling from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region. An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Takeshi SAKAI, Akihiro HANADA, Masahiro WATABE
  • Publication number: 20250093282
    Abstract: A soil sensor includes a first signal line transmitting a high-frequency electromagnetic wave, and a porous body having a water permeability and a water retention property. The soil sensor further includes a second signal line transmitting a low-frequency electromagnetic wave and facing soil through the porous body, and a ground line arranged on an inside of the first signal line. The second signal line is arranged on an inside of the first signal line and the ground line. Thus, the first signal line and the second signal line are prevented from causing an influence to each other by an electric field generated by one of the two lines.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Minekazu SAKAI, Naohisa NIIMI, Norihiro KURUMADO, Tomohide ARIKI, Kei SHIMAKURA, Keita NAMBARA, Masashi SUZUKI, Hidetada KAJINO, Naoki HASHIMOTO
  • Patent number: 12220394
    Abstract: The present invention pertains to a pharmaceutical composition for the prevention or treatment of kidney disease, a kidney inflammation inhibitor, an inflammatory cell death inhibitor for the kidneys, or a food for the prevention or improvement of kidney disease, that include D-alanine or a derivative thereof. In addition, the present invention pertains to the use of D-alanine or a derivative thereof, for the production of a pharmaceutical composition for the prevention or treatment of kidney disease.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 11, 2025
    Assignees: National University Corporation Kanazawa University, Kagami Inc.
    Inventors: Takashi Wada, Kengo Furuichi, Norihiko Sakai, Yasunori Iwata, Akinori Hara, Yusuke Nakade, Kenji Hamase, Masashi Mita
  • Publication number: 20250048562
    Abstract: A wiring substrate includes a core substrate including a glass substrate and a through-hole conductor, a resin insulating layer having an opening extending through the resin insulating layer, a conductor layer including a seed layer and an electrolytic plating layer on the seed layer, and a via conductor formed in the opening such that the via conductor electrically connects to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The resin insulating layer includes resin and inorganic particles including first and second particles such that the first particles are partially embedded in the resin and that the second particles are embedded in the resin, the first particles have first portions protruding from the resin and second portions embedded in the resin respectively, the surface includes the resin and exposed surfaces of the first portions exposed from the resin.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 6, 2025
    Applicant: IBIDEN CO., LTD.
    Inventors: Masashi KUWABARA, Susumu KAGOHASHI, Jun SAKAI, Kyohei YOSHIKAWA, Takuya INISHI
  • Patent number: 12209030
    Abstract: Provide is a solid electrolyte material represented by a composition formula LiaYbMcX6-dFd, where M includes at least one kind selected from the group consisting of metalloid elements and metal elements other than Li and Y; X is at least one kind selected from the group consisting Cl, Br, and I; 0<a; 0<b; 0?c; and 0<d<6.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: January 28, 2025
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masashi Sakaida, Tetsuya Asano, Akihiro Sakai, Yusuke Nishio, Akinobu Miyazaki, Shinya Hasegawa
  • Patent number: 11948794
    Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: April 2, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masashi Sakai, Takuma Mizobe, Takuyo Nakamura
  • Publication number: 20230253372
    Abstract: A semiconductor device includes a plurality of arms each including: a heat dissipation plate; a switching element; a metal terminal; and a sealing material, the metal terminals of the two specific arms adjacent to each other in the first direction has a first protruding portion which protrudes from a portion of the sealing material on one side in the second direction, the first protruding portion of one specific arm is arranged on a side closer to the other specific arm than a center portion in the first direction is, at the portion of the sealing material on the one side in the second direction, and the first protruding portion of the other specific arm is arranged on a side closer to the one specific arm than a center portion in the first direction is, at the portion of the sealing material on the one side in the second direction.
    Type: Application
    Filed: August 22, 2022
    Publication date: August 10, 2023
    Inventors: Masashi SAKAI, Masakazu TANI
  • Patent number: 11694948
    Abstract: This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: July 4, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masashi Sakai
  • Publication number: 20220328384
    Abstract: This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.
    Type: Application
    Filed: October 20, 2021
    Publication date: October 13, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventor: Masashi SAKAI
  • Publication number: 20220028688
    Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.
    Type: Application
    Filed: April 27, 2021
    Publication date: January 27, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masashi SAKAI, Takuma MIZOBE, Takuyo NAKAMURA
  • Patent number: 11233126
    Abstract: A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5×1014/cm3 or more and 2×1016/cm3 or less.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 25, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masashi Sakai, Yoichiro Mitani
  • Publication number: 20210010158
    Abstract: Provided are a silicon carbide epitaxial growth device capable of fostering epitaxial growth on a silicon carbide substrate. Mounting a wafer holder loaded with a silicon carbide substrate and a tantalum carbide member to a turntable in a susceptor, and supplying a growth gas, a doping gas, and a carrier gas into the susceptor by heating by induction heating coils placed around the susceptor, thereby epitaxial growth is fostered, and stable and proper device characteristics are obtained, moreover, the yield in a manufacturing step of the silicon carbide epitaxial wafer is significantly improved.
    Type: Application
    Filed: April 29, 2020
    Publication date: January 14, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masashi SAKAI, Shinichiro KATSUKI, Kazuo KOBAYASHI, Yasunari HINO
  • Patent number: 10886184
    Abstract: The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: January 5, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuyo Nakamura, Masashi Sakai
  • Publication number: 20200321437
    Abstract: A silicon carbide epitaxial wafer includes a silicon carbide substrate and silicon carbide epitaxial layers formed on the silicon carbide substrate. Each of the silicon carbide epitaxial layers has a triangular defect. The silicon carbide epitaxial layer each have a step inside the triangular defect in the surface morphology of the triangular defect.
    Type: Application
    Filed: January 15, 2020
    Publication date: October 8, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masashi SAKAI, Yoichiro MITANI, Takuyo NAKAMURA
  • Publication number: 20200279922
    Abstract: A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5×1014/cm3 or more and 2×1016/cm3 or less.
    Type: Application
    Filed: December 18, 2019
    Publication date: September 3, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masashi SAKAI, Yoichiro MITANI
  • Patent number: 10707075
    Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Masashi Sakai, Yasuhiro Kimura, Yoichiro Mitani, Takashi Kanazawa
  • Publication number: 20200144053
    Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 7, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenichi HAMANO, Akihito OHNO, Takuma MIZOBE, Masashi SAKAI, Yasuhiro KIMURA, Yoichiro MITANI, Takashi KANAZAWA
  • Publication number: 20190221485
    Abstract: The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.
    Type: Application
    Filed: October 23, 2018
    Publication date: July 18, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuyo NAKAMURA, Masashi SAKAI
  • Patent number: 10084388
    Abstract: A power converter includes: a base conductor, an electrically heating member which is provided on the base conductor, a noise reduction capacitor of flat plate-shape in which via an insulator, a plurality of first electrodes and second electrodes are alternately layered, on one surface, the first electrode in an outermost layer is exposed and on another surface, the second electrode in an outermost layer is exposed, a relay conductor which is electrically connected to other members from the electrically heating member via the noise reduction capacitor, and the second electrode in an outermost layer of the noise reduction capacitor is face-joined to a face of the base conductor at a side where the electrically heating member is provided and the first electrode in an outermost layer and the relay conductor are face-joined.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: September 25, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keita Takahashi, Kazuki Sakata, Yoshiyuki Deguchi, Takuto Yano, Mamoru Takikita, Kazutoshi Awane, Koji Nakajima, Takao Mitsui, Kosuke Nakano, Masayoshi Tamura, Masashi Sakai
  • Publication number: 20170194873
    Abstract: A power converter includes: a base conductor, an electrically heating member which is provided on the base conductor, a noise reduction capacitor of flat plate-shape in which via an insulator, a plurality of first electrodes and second electrodes are alternately layered, on one surface, the first electrode in an outermost layer is exposed and on another surface, the second electrode in an outermost layer is exposed, a relay conductor which is electrically connected to other members from the electrically heating member via the noise reduction capacitor, and the second electrode in an outermost layer of the noise reduction capacitor is face-joined to a face of the base conductor at a side where the electrically heating member is provided and the first electrode in an outermost layer and the relay conductor are face-joined.
    Type: Application
    Filed: June 12, 2015
    Publication date: July 6, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keita TAKAHASHI, Kazuki SAKATA, Yoshiyuki DEGUCHI, Takuto YANO, Mamoru TAKIKITA, Kazutoshi AWANE, Koji NAKAJIMA, Takao MITSUI, Kosuke NAKANO, Masayoshi TAMURA, Masashi SAKAI