Abstract: A device and method for implementing prediction verification control and recovery control in speculative instruction execution when a prediction error occurs with simple hardware configuration are disclosed. This device includes a branch instruction insertion unit that dynamically inserts a branch instruction subsequent to a target instruction for prediction in a group of instructions consisting of the target instruction for prediction for which a value is to be predicted and a subsequent instruction. An instruction issuing unit speculatively issues a subsequent instruction to an execution unit without waiting for the execution result of the target instruction for prediction and an execution unit executes the issued instructions.

Abstract: One transfer request is selected from a plurality of transfer requests. The end time of a transfer process corresponding to an identifier attached to the selected transfer request is set. If the set end time elapses during the data transfer process based on the selected transfer request, the selected transfer request is erased.

Abstract: An apparatus and method which verify a system including a microprocessor. The apparatus includes first and second simulators which verify a target architecture using a test program and a functional description of the system, respectively. The first and second simlators extract first event information that expresses a verification item relating to a specification of the system. Further, checkers compare results of verification run by the second simulator with results of verification run by the first simulator. The first and second simulators execute an identification of the verification item. The checkers further examine a coverage of the system on the basis of second event information extracted from the verification item with the first event information, if the results of the verification run by the first simulator match the results of the verification run by the second simulator. The second event information is annotation data that describes information on events based on a specification for the system.

Abstract: A microprocessor capable of suppressing reduction in performance caused due to a cache miss when a specific command is issued. The processor according to the present invention comprises a command buffer/queue; an execution unit; a subroutine call decoder; a data cache control unit; an Addiu decoder for detecting an addiu command; a pre-fetch control section; an adder; a PAdr register; a selector; and an adder circuit. When a subroutine call occurs, a stack pointer is moved by an amount used in a subroutine, and data used in the subroutine is pre-fetched to be stored in an area used by the subroutine in a data cache. Therefore, it is possible to reduce cache miss penalties due to stack access which is apt to be generated at the time of a subroutine call.

Abstract: A device and method for implementing prediction verification control and recovery control in speculative instruction execution when a prediction error occurs with simple hardware configuration are disclosed. This device includes a branch instruction insertion unit that dynamically inserts a branch instruction subsequent to a target instruction for prediction in a group of instructions consisting of the target instruction for prediction for which a value is to be predicted and a subsequent instruction. An instruction issuing unit speculatively issues a subsequent instruction to an execution unit without waiting for the execution result of the target instruction for prediction and an execution unit executes the issued instructions.

Abstract: An apparatus which verifies a system comprising at least a microprocessor includes a first simulator which verifies a test program for the system. The apparatus further includes a second simulator which verifies a functional description of the system to extract first event information that expresses a verification item relating to an operational specification of the system, as an event. The apparatus further includes a comparator which compares results of verification carried out by the second simulator with results of verification carried out by the first simulator, and a checker which checks whether or not the verification item is met on the basis of a second event information resulting from the verification carried out by the second simulator and the first event information if the results of the verification carried out by the first simulator match the results of the verification carried out by the second simulator.

Abstract: A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.

Abstract: There is disclosed DTLB in a microprocessor of the present invention, comprising an adder for adding a base address and a sign-extended offset address; a comparator for judging whether or not upper side 20 bits [31:12] of the base address match the base address stored in a upper side address storage section in CAM 35, and upper side 4 bits [15:12] of the offset address match the offset address stored in the CAM; a comparator for judging whether or not a carry signal outputted from the adder and a carry signal stored in a carry storage section in the CAM are matched; and a match detector for outputting a match signal when comparison results of the comparators are matched. With lower side 12 bits of the virtual address, the judgment of match/mismatch is performed only with the carry signal. Therefore, the match/mismatch of the virtual address can be judged before the addition processing in the adder is completed.

Abstract: It is an object of the present invention to provide a microprocessor capable of suppressing reduction in performance caused due to a cache miss when a specific command is issued. The processor according to the present invention comprises a command buffer/queue; an execution unit; a subroutine call decoder; a data cache control unit; an Addiu decoder for detecting an addiu command; a pre-fetch control section; an adder; a PAdr register; a selector; and an adder circuit. When a subroutine call occurs, a stack pointer is moved by an amount used in a subroutine, and data used in the subroutine is pre-fetched to be stored in an area used by the subroutine in a data cache. Therefore, it is possible to reduce cache miss penalties due to stack access which is apt to be generated at the time of a subroutine call.