Patents by Inventor Masashi Takata

Masashi Takata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953220
    Abstract: A comfort-analyzing device includes a display unit, a first control unit, an input unit, and a cognitive-structure constructing unit. The display unit is configured to present a questionnaire for extracting both a comfort level of a user in an environment and at least one environmental factor to determine the comfort level. The first control unit is configured to cause the display unit to present the questionnaire twice or more during a survey period. The input unit is configured to accept, from the user, input of each reply to the questionnaire presented twice or more. The cognitive-structure constructing unit is configured to construct a cognitive-structure model representing a cognitive structure of the user regarding comfort by extracting both the comfort level and the at least one environmental factor in chronological order based on each reply to the questionnaire presented twice or more.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: April 9, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kota Kurihara, Seiro Yuge, Makoto Takata, Noriko Nagata, Masashi Sugimoto
  • Patent number: 10074336
    Abstract: The voltage transmission circuit includes: a multiplexer for transmitting positive and negative voltages ranging +VDD to ?VDD selectively; and a demultiplexer for receiving the positive and negative voltages and output them at positive and negative outputs. The voltage transmission circuit is arranged by use of elements each having a withstand voltage of which the absolute value is not 2|VDD|, but |VDD|. While transmitting positive voltages, the multiplexer is configured not to be applied by negative voltages, the multiplexer and demultiplexer are controlled by signals each having a potential of 0 V to +VDD, and the demultiplexer outputs the positive voltages at the positive output. While transmitting negative voltages, the multiplexer is configured not to be applied by positive voltages, the multiplexer and the demultiplexer are controlled by signals each having a potential of ?VDD to 0 V, and the demultiplexer outputs the negative voltages at the negative output.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: September 11, 2018
    Assignee: Synaptics Japan GK
    Inventors: Masashi Takata, Shigeki Ueda, Norihiro Enomoto
  • Patent number: 9601043
    Abstract: The display device includes display drivers including first and second ones operable to output, based on display data, gradation signals to source lines of display panel regions. The display device is arranged to be able to suppress the variation in output voltage between display drivers while minimizing the increases in chip area of the display drivers and in wiring area of a display panel and keeping high noise resistance. Each display driver can generate gray scale reference voltages for producing gradation signals corresponding to display data. The first display driver can sequentially transmit gray scale reference voltages generated by itself to the second display driver. Based on the transmitted gray scale reference voltages, the second display driver makes the first display driver execute calibration for decreasing the absolute value of difference between gray scale reference voltages generated by the first and second display drivers, or executes the calibration by itself.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 21, 2017
    Assignee: Synaptics Japan GK
    Inventors: Toshiyuki Hikichi, Yasuhito Kurokawa, Shutaro Ichikawa, Masashi Takata
  • Publication number: 20160012794
    Abstract: The voltage transmission circuit includes: a multiplexer for transmitting positive and negative voltages ranging +VDD to ?VDD selectively; and a demultiplexer for receiving the positive and negative voltages and output them at positive and negative outputs. The voltage transmission circuit is arranged by use of elements each having a withstand voltage of which the absolute value is not 2|VDD|, but |VDD|. While transmitting positive voltages, the multiplexer is configured not to be applied by negative voltages, the multiplexer and demultiplexer are controlled by signals each having a potential of 0 V to +VDD, and the demultiplexer outputs the positive voltages at the positive output. While transmitting negative voltages, the multiplexer is configured not to be applied by positive voltages, the multiplexer and the demultiplexer are controlled by signals each having a potential of ?VDD to 0 V, and the demultiplexer outputs the negative voltages at the negative output.
    Type: Application
    Filed: June 23, 2015
    Publication date: January 14, 2016
    Inventors: Masashi TAKATA, Shigeki UEDA, Norihiro ENOMOTO
  • Publication number: 20150109348
    Abstract: The display device includes display drivers including first and second ones operable to output, based on display data, gradation signals to source lines of display panel regions. The display device is arranged to be able to suppress the variation in output voltage between display drivers while minimizing the increases in chip area of the display drivers and in wiring area of a display panel and keeping high noise resistance. Each display driver can generate gray scale reference voltages for producing gradation signals corresponding to display data. The first display driver can sequentially transmit gray scale reference voltages generated by itself to the second display driver. Based on the transmitted gray scale reference voltages, the second display driver makes the first display driver execute calibration for decreasing the absolute value of difference between gray scale reference voltages generated by the first and second display drivers, or executes the calibration by itself.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 23, 2015
    Inventors: Toshiyuki Hikichi, Yasuhito Kurokawa, Shutaro Ichikawa, Masashi Takata