Patents by Inventor Masashi Takenaka
Masashi Takenaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9355974Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: GrantFiled: August 17, 2015Date of Patent: May 31, 2016Assignee: SOCIONEXT INC.Inventors: Masashi Takenaka, Katsuyoshi Yamamoto
-
Publication number: 20150357299Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Masashi Takenaka, Katsuyoshi Yamamoto
-
Patent number: 9142516Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: GrantFiled: June 18, 2012Date of Patent: September 22, 2015Assignee: SOCIONEXT INC.Inventors: Masashi Takenaka, Katsuyoshi Yamamoto
-
Publication number: 20130026649Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: ApplicationFiled: June 18, 2012Publication date: January 31, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masashi Takenaka, Katsuyoshi Yamamoto
-
Patent number: 7564111Abstract: In an imaging apparatus constituted of a case body for mounting an imaging device and a flexible substrate bonding to an external connection terminal provided on the case body, the flexible substrate is bent along each face of case body 41 so as to surround case body 41. By bending the flexible substrate, a load applied to the flexible substrate is received at the bent portion of the flexible substrate, there is formed a structure hard to transmit the load to the bonding portion to the external connection terminal. Further, by fixing the case body to a portion of the flexible substrate with an adhesive agent, etc., there is formed a structure not to transmit a stress to the direction of peeling the flexible substrate from the external connection terminal. Also, the case body is covered with the flexible substrate equipped with an electromagnetic wave shield material.Type: GrantFiled: January 25, 2007Date of Patent: July 21, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Koji Sawahata, Susumu Moriya, Hiroshi Aoki, Izumi Kobayashi, Toshiyuki Honda, Shigeo Iriguchi, Masashi Takenaka
-
Publication number: 20070120050Abstract: In an imaging apparatus constituted of a case body for mounting an imaging device and a flexible substrate bonding to an external connection terminal provided on the case body, the flexible substrate is bent along each face of case body 41 so as to surround case body 41. By bending the flexible substrate, a load applied to the flexible substrate is received at the bent portion of the flexible substrate, there is formed a structure hard to transmit the load to the bonding portion to the external connection terminal. Further, by fixing the case body to a portion of the flexible substrate with an adhesive agent, etc., there is formed a structure not to transmit a stress to the direction of peeling the flexible substrate from the external connection terminal. Also, the case body is covered with the flexible substrate equipped with an electromagnetic wave shield material.Type: ApplicationFiled: January 25, 2007Publication date: May 31, 2007Inventors: Koji Sawahata, Susumu Moriya, Hiroshi Aoki, Izumi Kobayashi, Toshiyuki Honda, Shigeo Iriguchi, Masashi Takenaka
-
Publication number: 20070114642Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: ApplicationFiled: January 19, 2007Publication date: May 24, 2007Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
-
Patent number: 7193320Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: GrantFiled: January 28, 2003Date of Patent: March 20, 2007Assignee: Fujitsu LimitedInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
-
Patent number: 6881611Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.Type: GrantFiled: August 8, 2000Date of Patent: April 19, 2005Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Toshimi Kawahara, Muneharu Morioka, Mitsunada Osawa, Yasuhiro Shinma, Hirohisa Matsuki, Masanori Onodera, Junichi Kasai, Shigeyuki Maruyama, Masao Sakuma, Yoshimi Suzuki, Masashi Takenaka
-
Publication number: 20030222344Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: ApplicationFiled: January 28, 2003Publication date: December 4, 2003Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
-
Publication number: 20020030258Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.Type: ApplicationFiled: January 23, 2001Publication date: March 14, 2002Applicant: FUJITSU LIMITEDInventors: Norio Fukasawa, Toshimi Kawahara, Muneharu Morioka, Mitsunada Osawa, Yasuhiro Shinma, Hirohisa Matsuki, Masanori Onodera, Junichi Kasai, Shigeyuki Maruyama, Masao Sakuma, Yoshimi Suzuki, Masashi Takenaka
-
Patent number: 6347037Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.Type: GrantFiled: November 4, 1998Date of Patent: February 12, 2002Assignee: Fujitsu LimitedInventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi, Masaru Nukiwa, Takao Akai
-
Patent number: 6342729Abstract: A tape carrier package formed by a TAB technique is provided. This tape carrier package includes a semiconductor chip and a TAB tape. The TAB tape has a rectangular device hole in which the semiconductor chip is situated, and inner leads extending inward in the device hole and bonded to the electrode bumps of the semiconductor chip. The inner leads (corner leads) at each corner of the device holes are reinforced by reinforcing leads.Type: GrantFiled: June 30, 1999Date of Patent: January 29, 2002Assignee: Fujitsu LimitedInventors: Masashi Takenaka, Shiro Yoda, Junichiro Hiyoshi, Hiroshi Takahashi, Hideo Sato
-
Publication number: 20020001178Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.Type: ApplicationFiled: November 4, 1998Publication date: January 3, 2002Inventors: MAKOTO IIJIMA, TETSUSHI WAKABAYASHI, TOSHIO HAMANO, MASAHARU MINAMIZAWA, MASASHI TAKENAKA, TATUROU YAMASHITA, MASATAKA MIZUKOSHI, MASARU NUKIWA, TAKAO AKAI
-
Patent number: 6268645Abstract: A semiconductor device having a semiconductor chip on a TAB (Tape Automated Bonding) tape with high reliability is provided. The semiconductor device of the present invention includes a TAB tape which has a base film provided with a device hole in a position where a semiconductor chip is mounted, a wiring pattern whose end portions constitute inner leads connected to the semiconductor chip and terminal connecting portions provided with solder balls, and a photo-solder resist which protects the wiring pattern. Chamfered portions which relieves internal residual stress caused in the photo-solder resist due to the difference in thermal expansion coefficient between the base film and the photo-solder resist are formed at locations on the photo-solder resist facing the corners of the device hole.Type: GrantFiled: March 22, 2000Date of Patent: July 31, 2001Assignee: Fujitsu LimitedInventors: Masashi Takenaka, Shiro Yoda, Junichiro Hiyoshi, Hiroshi Takahashi, Hideo Sato
-
Publication number: 20010003049Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.Type: ApplicationFiled: May 15, 1998Publication date: June 7, 2001Inventors: NORIO FUKASAWA, TOSHIMI KAWAHARA, MUNEHARU MORIOKA, MITSUNADA OSAWA, YASUHIRO SHINMA, HIROHISA MATSUKI, MASANORI ONODERA, JUNICHI KASAI, SHIGEYUKI MARUYAMA, MASAO SAKUMA, YOSHIMI SUZUKI, MASASHI TAKENAKA
-
Patent number: 6184133Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.Type: GrantFiled: February 18, 2000Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
-
Patent number: 6088233Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.Type: GrantFiled: November 18, 1998Date of Patent: July 11, 2000Assignee: Fujitsu LimitedInventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
-
Patent number: 5978222Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.Type: GrantFiled: September 8, 1997Date of Patent: November 2, 1999Assignee: Fujitsu LimitedInventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
-
Patent number: 5920117Abstract: A semiconductor device includes a board having a lower surface, a container part created in the board, external-connection nodes provided on the lower surface of the board, a supporting member provided inside the container part and secured by the board, a semiconductor chip secured on the supporting member and electrically connected with the external-connection nodes, and a sealing resin fully filling the container part so as to completely cover the semiconductor chip.Type: GrantFiled: March 18, 1997Date of Patent: July 6, 1999Assignee: Fujitsu LimitedInventors: Michio Sono, Masashi Takenaka, Masanori Yoshimoto, Tsuyoshi Aoki, Ichiro Yamaguchi, Koki Otake