Patents by Inventor Masashi UECHA

Masashi UECHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162092
    Abstract: A manufacturing method of a semiconductor device includes: forming a plurality of element structures in a form of matrix on a first surface of a semiconductor wafer; forming a crack extending in a thickness direction of the semiconductor wafer along a boundary between the element structures adjacent to each other by pressing a pressing member against a second surface of the semiconductor wafer opposite to the first surface along the boundary; and dividing the semiconductor wafer along the boundary by pressing a dividing member against the semiconductor wafer on a first surface side along the boundary.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 16, 2024
    Inventors: Yuji NAGUMO, Masashi UECHA, Masaru OKUDA, Masatake NAGAYA, Mitsuru KITAICHI, Akira MORI, Naoya KIYAMA, Masakazu TAKEDA
  • Publication number: 20240038711
    Abstract: A semiconductor device includes a semiconductor substrate and a metal layer disposed on a surface of the semiconductor substrate. The metal layer includes a first metal layer and a second metal layer. The second metal layer covers a surface of the first metal layer and has a higher solder wettability than the first metal layer. The second metal layer is exposed on a main surface of the metal layer. The first metal layer is exposed on a side surface of the metal layer. The metal layer has a protruding portion on the main surface. The protruding portion extends to make one round along an outer peripheral edge of the main surface.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: TERUAKI KUMAZAWA, MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA
  • Publication number: 20240038590
    Abstract: A semiconductor device includes a semiconductor substrate having a quadrangular shape when viewed from above and having a front surface, a rear surface opposite to the front surface, and four side surfaces connecting the front surface and the rear surface. Each of the side surfaces has a step section in which a plurality of protruding portions and a plurality of recessed portions alternately and repeatedly appear along a direction in which a peripheral edge of the front surface of the semiconductor substrate extends.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA
  • Publication number: 20240030056
    Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate having a plurality of element regions and having a first surface and a second surface opposite to each other, forming a crack extending in a thickness direction of the semiconductor substrate along a boundary between the plurality of element regions by pressing a pressing member against the first surface of the semiconductor substrate along the boundary, forming a metal film over the plurality of element regions on the first surface of the semiconductor substrate after the forming of the crack, and dividing the semiconductor substrate and the metal film along the boundary by pressing a dividing member against the semiconductor substrate along the boundary from a direction facing the second surface of the semiconductor substrate after the forming of the metal film.
    Type: Application
    Filed: May 26, 2023
    Publication date: January 25, 2024
    Inventors: MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA
  • Publication number: 20230268185
    Abstract: A manufacturing method of a semiconductor device, includes: preparing a wafer having a first surface on which a plurality of semiconductor elements is formed and to which a support plate is attached through an adhesive; grinding a second surface of the wafer opposite to the first surface in a state where the support plate is attached to the first surface of the wafer; forming a vertical crack inside the wafer and along a boundary between the adjacent semiconductor elements by pressing a scribe wheel against the wafer along the boundary; separating the support plate from the wafer while leaving the adhesive on the first surface of the wafer; cleaving the wafer along the boundary by pressing a breaking bar against the wafer over the adhesive and along the boundary; and removing the adhesive from at least one of the semiconductor elements divided from the wafer by the cleaving.
    Type: Application
    Filed: January 19, 2023
    Publication date: August 24, 2023
    Inventors: Hiroyuki TAKAHATA, Yuji NAGUMO, Masashi UECHA
  • Publication number: 20230268230
    Abstract: In a manufacturing method of a semiconductor device, a wafer in which multiple semiconductor elements is formed and having a first surface and a second surface opposite to each other is prepared, and a groove is formed on the first surface of the wafer along a boundary between adjacent semiconductor elements in the multiple semiconductor elements. The wafer is attached to a support plate in such a manner that the first surface of the wafer faces the support plate, and a scribing blade is pressed against the second surface of the wafer along the boundary to form a vertical crack inside the wafer along the boundary. Then, a breaking blade is pressed against the wafer along the boundary to cleave the wafer along the boundary.
    Type: Application
    Filed: January 24, 2023
    Publication date: August 24, 2023
    Inventors: FUMIHITO TACHIBANA, MASASHI UECHA, YUJI NAGUMO
  • Publication number: 20230197519
    Abstract: In a manufacturing method of a semiconductor device, a semiconductor wafer that is made of a semiconductor material harder than silicon and has a first surface and a second surface opposite to each other is prepared, a roughened layer is formed by grinding the second surface of the semiconductor wafer, a blade is pressed against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer, the roughened layer is removed after the vertical crack is formed, a rear surface electrode is formed on a rear surface of the semiconductor wafer on which the vertical crack is formed, and after the rear surface electrode is formed, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is cleaved into multiple pieces with the vertical crack as a starting point.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Inventors: YUJI NAGUMO, MASASHI UECHA, HIROKI TSUMA, TERUAKI KUMAZAWA
  • Publication number: 20230178497
    Abstract: A semiconductor device includes a semiconductor substrate, an end region, and an active region. The end region is located above the semiconductor substrate, has a frame shape, and has been brought into contact with a blade in a scribing process. The active region is surrounded by the end region and is configured to serve as a path of a main current. The end region has a stress relaxation film on an outermost surface of the end region.
    Type: Application
    Filed: November 15, 2022
    Publication date: June 8, 2023
    Inventors: Masashi UECHA, Yuji NAGUMO, Hiroki TSUMA, Teruaki KUMAZAWA
  • Publication number: 20230154987
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer and a side silicide layer. The silicon carbide semiconductor layer includes a silicon carbide single crystal and has a main surface, a rear surface opposite to the main surface, and a side surface connecting the main surface and the rear surface and formed by a cleavage plane. The silicon carbide semiconductor layer further includes a modified layer. The modified layer forms a part of the side surface located close to the rear surface and has an atomic arrangement structure of silicon carbide different from an atomic arrangement structure of the silicon carbide single crystal. The side silicide layer includes a metal silicide that is a compound of a metal element and silicon. The side silicide layer is disposed on the side surface of the silicon carbide semiconductor layer and is adjacent to the modified layer.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 18, 2023
    Inventors: HIROKI TSUMA, YUJI NAGUMO, MASASHI UECHA, TERUAKI KUMAZAWA
  • Publication number: 20230009078
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes formation of an electrode and formation of a gate wiring. The electrode is formed to be electrically connected to a base layer and an impurity region included in a semiconductor substrate through a first contact hole. The gate wiring is formed to be electrically connected to a connection wiring through a second contact hole, and is made of material capable of deoxidizing an oxide film. The oxide film is removed by deoxidizing the oxide film formed on the connection wiring to remove the oxygen from the oxide film into the gate wiring through heating treatment for the gate wiring in the formation of the gate wiring or after the formation of the gate wiring.
    Type: Application
    Filed: June 28, 2022
    Publication date: January 12, 2023
    Inventors: Hiroki TSUMA, Yohei IWAHASHI, Masashi UECHA