Abstract: A shift register includes series-connection circuits to transmit a shift pulse. The series-connection circuits include a continuous stage group with continuous stages. Each stage of the continuous stage group includes a first output transistor, a first capacitor, an input gate, a first switching element, a second switching element, a third switching element, and a fourth switching element.

Abstract: A multi-primary color display device is capable of handling an increased number of primary colors for color image display with a reduced number of external parts, with reduced increase in the amount of drive circuit and reduced increase in operating speed. An active matrix liquid crystal panel includes a display section constituted by pixel formation portions, each made of four sub pixel-formation portions which handle four primary colors. These four sub pixel-formation portions are arranged in a 2×2 matrix pattern. With such a pixel configuration, a source driver drives as many as M source lines, which is two times the number M of pixels arranged in a horizontal direction. A gate driver is formed on the liquid crystal panel integrally with pixel circuit in the display section, and drives as many as N gate lines, which is two times the number N of the pixels arranged in a vertical direction.

Abstract: Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal.

Abstract: To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element.

Abstract: A bistable circuit includes an output terminal that outputs a state signal, an output terminal that outputs an other-stage control signal, a first node of which a potential is controlled based on a set signal and a clear signal, a thin-film transistor that provides a potential of a second clock to the output terminal when a potential of the first node is at a high level, a thin-film transistor that provides a potential of a first clock to the output terminal when a potential of the first node is at a high level, and a thin-film transistor for changing a potential of the other-stage control signal to a low level based on a reset signal. The first clock is generated by a power source of a different system from the second clock, and has a smaller amplitude than that of the second clock.

Abstract: Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. In at least one example embodiment, each stage of the shift register includes a first output transistor, a second output transistor, a first capacitor, a second capacitor, an input gate, a first switching element, a second switching element, a third switching element, a fourth switching element, and a fifth switching element.

Abstract: Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal.

Abstract: An object of the present invention is to provide a multi-primary color display device which is capable of handling an increased number of primary colors for color image display with a reduced number of external parts, with reduced increase in the amount of drive circuit and reduced increase in operating speed. An active matrix liquid crystal panel (600) includes a display section (500) constituted by pixel formation portions, each made of four sub pixel-formation portions (Ps) which handle four primary colors. These four sub pixel-formation portions are arranged in a 2×2 matrix pattern. With such a pixel configuration, a source driver (300) drives as many as M source lines (Ls), which is two times the number Mpix of pixels arranged in a horizontal direction. A gate driver (400) is formed on the liquid crystal panel (600) integrally with pixel circuit in the display section (500), and drives as many as N gate lines (Lg), which is two times the number Npix of the pixels arranged in a vertical direction.

Abstract: A gate driver is implemented that includes an easily testable shift register to improve panel yields. In a monolithic gate driver including a shift register that operates based on 4-phase clock signals, each stage of the shift register is provided with an inter-stage connecting wiring line for receiving a clock signal other than clock signals received from a clock signal trunk wiring line, from a different stage than the stage; and a contact that connects a wiring line formed on the stage to the inter-stage connecting wiring line. The shift register is grouped every four consecutive stages. Markings formed of different numbers of planar-view circular-shaped structures are formed on bistable circuits of four stages included in each group such that the same type of marking appears every four stages.

Abstract: To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element.

Abstract: Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. Each stage (Xi) of the shift register includes a first output transistor (M5), a second output transistor (M7), a first capacitor (C1), a second capacitor (C2), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), a fourth switching element (M6), and a fifth switching element (M8).

Abstract: Each stage (Xi) of a shift register includes a first output transistor (M5), a first capacitor (C1), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), and a fourth switching element (M6).

Abstract: A semiconductor integrated circuit is provided, which comprises a first cell comprising a plurality of transistors, a second cell comprising a PMOS transistor section and an NMOS transistor section, the PMOS transistor section comprising a first PMOS transistor and a second PMOS transistor connected to the first PMOS transistor in series, the NMOS transistor section comprising a first NMOS transistor and a second NMOS transistor connected to the first NMOS transistor in series. A predetermined scheme is used to connect between the first cell and the second cell, between the plurality of transistors in the first cell, and between the PMOS transistor section and the NMOS transistor section in the second cell.

Abstract: A semiconductor integrated circuit includes a signal output circuit including a first switching device and a second switching device; and a third switching device. The first switching device is supplied with a first voltage via the third switching device. The second switching device is supplied with a second voltage. The signal output circuit receives a first binary signal, and outputs at least one of two values of a second binary signal based on the first binary signal, the first voltage and the second voltage. The third switching device receives a control signal for controlling the third switching device to be in an ON state or in an OFF state; and when the third switching device is in the OFF state, the third switching device turns OFF the supply of the first voltage to the first switching device.

Abstract: A semiconductor integrated circuit of the present invention includes MOSFETs of at least one of N channel- and P channel-types where at least two MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes two serially-connected MOSFETs of the same channel-type in which their respective gates are connected to each other.

Abstract: A semiconductor integrated circuit includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.

Abstract: A semiconductor integrated circuit of the present invention includes MOSFETs of at least one of N channel- and P channel-types where at least two MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes two serially-connected MOSFETs of the same channel-type in which their respective gates are connected to each other.

Abstract: A semiconductor integrated circuit includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.

Abstract: A semiconductor integrated circuit of the present invention features that a voltage is stably applied to a cell for high-speed operation and the number of lengthy wirings which run around a cell row is reduced without increasing a chip area, so that line efficiency can be improved. Since a power source line 16 and a ground line 17, each having a wide line running width, are formed on a top line layer above a cell 1 so as to cover nearly the whole surface of the cell 1, electrical resistance of the power source line 16 and the ground line 17 is reduced and then the voltage applied to the cell for high-speed operation is stabilized and such design is enabled without increasing the chip area. In addition, since penetrating lines 18 and 19 are formed on the lower line layer on a border between the cells, the number of lengthy lines which run around the cell row can be reduced by using the penetrating lines 18 and 19 as connecting between cells, so that line efficiency can be improved.

Abstract: A serial-to-parallel type A/D converter includes a resistance array, a plurality of comparators for upper bits, a plurality of comparators for lower bits, an encoder for upper bits, an encoder for lower bits and an adder. The resistance array divides a predetermined reference voltage to generate upper reference voltages, and by dividing the step width of the upper reference voltage, generates lower reference voltages. The plurality of comparators for the upper bits compare the analog input signal with the upper reference voltages, and applies the result of comparison to the encoder for the upper bits. The encoder for the upper bits calculates an estimated value of the upper bits based on the result of comparison, and select second reference voltages in the range provided by adding .+-.1/2 LSB to 1LSB corresponding to the estimated value of the upper bits. The plurality of comparators for the lower bits calculate the lower bits and a correcting bit based on the selected second reference voltages.