Patents by Inventor Masashi Yoshida
Masashi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200286564Abstract: A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.Type: ApplicationFiled: September 12, 2019Publication date: September 10, 2020Applicant: Toshiba Memory CorporationInventors: Yuki SAKAGUCHI, Tatsuo Izumi, Masashi Yoshida
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Publication number: 20200241400Abstract: A projection optical projects from a first image plane on a reducing side onto a second image plane on a magnifying side includes: a first optical system with a plurality of lenses that forms a first intermediate image on a first side of an optical axis inside the first optical system by light that is incident from the reducing side, into a second intermediate image on a second side of the optical axis at a position closer to the magnifying side than the first optical system. A second optical system includes a first reflective surface with positive power that is positioned closer to the magnifying side than the second intermediate image. The first optical system includes an intermediate lens. The first intermediate image is formed to be inclined to be closer to the reducing side as a distance from the optical axis increases so as to straddle the intermediate lens.Type: ApplicationFiled: December 21, 2017Publication date: July 30, 2020Inventors: Masashi YOSHIDA, Takahiko MATSUO
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Publication number: 20200219595Abstract: According to one embodiment, a medical information display apparatus includes processing circuitry. The processing circuitry retrieves, based on subject patient information on a subject patient, similar-case patient information on a similar-case patient having a case similar to a case of the subject patient. The processing circuitry detects difference information of a difference between the subject patient information and the similar-case patient information which is equal to or greater than a first threshold. The processing circuitry causes the subject patient information and the similar-case patient information to be displayed and highlight the difference information.Type: ApplicationFiled: December 18, 2019Publication date: July 9, 2020Applicant: Canon Medical Systems CorporationInventor: Masashi YOSHIDA
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Patent number: 10685726Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.Type: GrantFiled: November 19, 2019Date of Patent: June 16, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuichiro Suzuki, Noboru Ooike, Masashi Yoshida
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Patent number: 10650267Abstract: According to one embodiment, a medical image processing apparatus includes a memory, an information collector and a determiner. The memory stores DICOM image data including study information. The information collector collects information relating to general-purpose image data incompatible with DICOM. The determiner determines whether designated general-purpose image data is related to a study which generates the DICOM image data, based on information collected by the information collector and the study information.Type: GrantFiled: January 20, 2016Date of Patent: May 12, 2020Assignee: Canon Medical Systems CorporationInventors: Masashi Yoshida, Kousuke Sakaue
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Publication number: 20200082893Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.Type: ApplicationFiled: November 19, 2019Publication date: March 12, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yuichiro SUZUKI, Noboru OOIKE, Masashi YOSHIDA
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Publication number: 20200013468Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a plurality of bit lines respectively connected to memory cells; a word line commonly connected to the memory cells; and a control circuit. The control circuit programs a first memory cell of a first state and a second memory cell of a second state by using a first program pulse. The control circuit applies a first voltage to a first bit line connected to the first memory cell, and applies a second voltage lower than the first voltage to a second bit line connected to the second memory cell at a first time within a first period during which the first program pulse is applied. The control circuit applies the second voltage to the first and second bit lines at a second time within the first period.Type: ApplicationFiled: March 6, 2019Publication date: January 9, 2020Applicant: Toshiba Memory CorporationInventors: Masashi Yoshida, Naofumi Abiko, Yoshikazu Harada
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Patent number: 10522233Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.Type: GrantFiled: January 11, 2018Date of Patent: December 31, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuichiro Suzuki, Noboru Ooike, Masashi Yoshida
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Patent number: 10268802Abstract: According to one embodiment, a medical image processing apparatus and a medical image processing system includes at least a position detecting unit, a human body chart storage unit, a mapping chart generating unit, and a display. A position detecting unit detects a position of a characteristic local structure in a human body from the medical image. A human body chart storage unit stores a human body chart that represents the human body. A mapping chart generating unit generates a mapping chart that is the human body chart to which a mark indicating a position of the local structure detected by the position detecting unit is added. A display displays the mapping chart.Type: GrantFiled: March 2, 2015Date of Patent: April 23, 2019Assignee: TOSHIBA MEDICAL SYSTEMS CORPORATIONInventors: Yosuke Yanagida, Junichi Tashiro, Jyunichi Yoshida, Kousuke Sakaue, Masashi Yoshida, Shigeyuki Ishii, Satoshi Ikeda, Hitoshi Yamagata, Takashi Masuzawa, Naoki Sugiyama, Muneyasu Kazuno
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Patent number: 10120052Abstract: In one embodiment, a medical image processing apparatus includes a display and processing circuitry. The processing circuitry is configured to (a) calculate fluid information including flow-velocity vectors based on three-dimensional image data of plural time phases, which are acquired by a phase contrast method of magnetic resonance imaging, and in which fluid flowing inside a lumen is depicted, (b) identify a branching position where a second lumen branches from a first lumen, based on change in flow volume of fluid flowing inside the first lumen along an extending direction of the first lumen, and (c) cause the display to display an analysis result including fluid information of fluid flowing inside the second lumen, based on the branching position.Type: GrantFiled: February 1, 2016Date of Patent: November 6, 2018Assignee: Toshiba Medical Systems CorporationInventors: Shuhei Bannae, Shigeharu Ohyu, Masashi Yoshida, Yoshihiro Ikeda, Fumiki Nakano, Mitsukazu Kamata, Tetsuya Yokota, Tatsuya Kimoto, Masao Yui, Tomohisa Fukunaga, Shigehide Kuhara, Kota Aoyagi
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Patent number: 10049760Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.Type: GrantFiled: March 15, 2017Date of Patent: August 14, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Tomoaki Nakano, Shigefumi Irieda, Masashi Yoshida
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Publication number: 20180137926Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Applicant: Toshiba Memory CorporationInventors: Yuichiro Suzuki, Noboru Ooike, Masashi Yoshida
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Publication number: 20180097395Abstract: An electronic device includes a charging unit, a maintaining unit, and a control unit. The charging unit charges a battery device with power supplied from a power supply line of an external cable. The maintaining unit maintains a connected state to a predetermined voltage of a specific line of the external cable by using power supplied from the power supply line. The control unit controls the maintaining unit so that the connected state is maintained by the maintaining unit, in a case where the charging unit is charging the battery device with power supplied from the power supply line when the electronic device is set to a power-off state.Type: ApplicationFiled: September 26, 2017Publication date: April 5, 2018Inventor: Masashi Yoshida
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Patent number: 9922268Abstract: According to one embodiment, an image interpretation report creating apparatus that creates an image interpretation report including a finding and is associated with a key image, includes a key image selecting unit, a position detecting unit, a first local structure information generating unit, and a display. A key image selecting unit selects a sub-image as the key image from among a plurality of sub-images comprising a medical image. A position detecting unit detects a position of a characteristic local structure in a human body from the medical image. A first local structure information generating unit identifies a local structure in the key image or in a vicinity of the key image and generates information on the identified local structure as first local structure information. A display displays the first local structure information as a candidate to be entered in an entry field for the finding.Type: GrantFiled: March 4, 2015Date of Patent: March 20, 2018Assignee: Toshiba Medical Systems CorporationInventors: Taisuke Iwamura, Kousuke Sakaue, Masashi Yoshida, Shigeyuki Ishii, Satoshi Ikeda, Hitoshi Yamagata, Takashi Masuzawa, Naoki Sugiyama, Muneyasu Kazuno, Yosuke Okubo, Hiroyuki Yamasaki, Jun Kawakami, Takashi Kondo, Guang Yi Ong
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Publication number: 20180068739Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.Type: ApplicationFiled: March 15, 2017Publication date: March 8, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro SHIINO, Tomoaki NAKANO, Shigefumi IRIEDA, Masashi YOSHIDA
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Patent number: 9905306Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.Type: GrantFiled: March 10, 2017Date of Patent: February 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuichiro Suzuki, Noboru Ooike, Masashi Yoshida
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Publication number: 20180054399Abstract: An information processing apparatus includes: an interface that receives detection data detected by a sensor terminal including one or more sensors that physically detect a condition of a dialogue partner, the detection data indicating a physical condition of the dialogue partner; and a controller that judges the condition of the dialogue partner from the received detection data, generates first-person statement data from the judged condition, generates a transmission message for an interactive-type SNS, that includes the statement data, and transmits the transmission message to a specific user on the interactive-type SNS.Type: ApplicationFiled: February 1, 2016Publication date: February 22, 2018Applicant: Sony CorporationInventors: Masataka Shinoda, Katsuhiko Takushige, Yuuki Watanabe, Masashi Yoshida, Daisuke Izaki
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Patent number: 9894844Abstract: The air emission device for growing plants includes a plurality of air emission units for respectively emitting an air flow onto the new leaves growing on a tip of a stem of each plant that has one stem. The transpiration effect on the leaves and suctioning of water and nutrition from the roots of the plants can be promoted. Thus, wilting of leaves can be prevented and the tip burn due to insufficient calcium can be avoided. Provision of the air emission units are effectively arranged to evenly or uniformly supply air onto the new leaves of the each plant.Type: GrantFiled: March 14, 2014Date of Patent: February 20, 2018Assignees: FUJI SEIKO CO., LTD., FUJI SHOJI CO., LTD.Inventors: Katsunori Takashima, Masashi Yoshida
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Publication number: 20180027747Abstract: The plant cultivation equipment which can perform planting work of seeds or seedlings without taking much labor and without attaching bacteria is disclosed. The plant cultivation equipment comprises a packing work room which includes a sterilization activity composition supply device which supplies the packing work room with a predetermined amount of sterilization activity composition which sterilizes the packing work space into which the packing materials are transferred, a sterilization activity composition detecting device provided in the packing work room and detecting the concentration of the sterilization activity composition, an exhaust device which discharges the sterilization activity composition from the packing work room and an outside air supply device which supplies the packing work room with the outside air through filter, capable of catching the sterilization activity composition, when the sterilization activity composition is discharged.Type: ApplicationFiled: February 18, 2015Publication date: February 1, 2018Applicants: FUJI SEIKO CO., LTD., FUJI SHOJI CO., LTD.Inventor: Masashi YOSHIDA
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Publication number: 20170271025Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.Type: ApplicationFiled: March 10, 2017Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuichiro SUZUKI, Noboru OOIKE, Masashi YOSHIDA