Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration H-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract: A semiconductor device includes a gate electrode 16 on a P type well through a gate oxide film 9, a heavily-doped N+ type source layer 12 formed to be adjacent to the one end of the gate electrode 16, an N+ type drain layer 12 formed apart from the other end of the gate electrode 16, a P type body layer 14 below the gate electrode 16, and a lightly-doped drain layer 10 formed in an area extending from below the gate electrode 16 to the heavily-doped N+ type drain layer 12 so that it is shallow at least below the gate electrode 16 and deep in the vicinity of the heavily-doped N-type drain layer 12.

Abstract: A P-channel type DMOS transistor includes heavily doped source/drain layers 12 formed in an N-type well 2, a gate electrode 18 formed on a channel layer located between the source/drain layers 12, an N-type body layer 14 formed in the vicinity of the source layer, and a lightly-doped drain layer 6 formed between the channel layer and the drain layer 12. In such a P-channel type DMOS transistor, a P-type layer 16 is formed in the channel layer at the upper part of the N-type body layer 14. In this configuration, the driving capability of the P-channel type DMOS transistor can be improved.

Abstract: A method for the production of a semiconductor integrated circuit device is disclosed, wherein the formation of lateral wall spacers for high voltage MOS transistor is implemented by forming a resist film for covering at least an insulating film formed on a drain region of low impurity concentration in the proximity of a gate electrode, masking the resist film, and etching the parts of the insulating film destined to give rise to the lateral wall spacers.

Abstract: An insulated gate field effect transistor fabricated in one conductivity type semiconductor substrate wherein a source region and a drain region are formed apart each other to define a channel region therebetween, having a deep ion implantation region which is so formed in the lower portion of the channel region that at least one end portion of the depletion region of the channel extends towards the source region beyond the border between the source region and the channel region at the surface of the substrate whereby an imaginary straight line drawn from said border at the surface of the substrate and an intersecting point between the depletion region of the source and the depletion region of the channel region without a back gate bias voltage defines an angle larger than 90.degree. against the surface of the substrate.